SFFSAL6 June   2025 OPA2991-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 VSSOP (DGK) | 8 Package
    2. 2.2 SOIC (D) | 8 Package
    3. 2.3 TSSOP (PW) | 8 Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 VSSOP (DGK) | 8 Package
    2. 4.2 SOIC (D) | 8 Package
    3. 4.3 TSSOP (PW) | 8 Package
  7. 5Revision History

Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the OPA2991-Q1 (VSSOP (DGK) | 8, SOIC (D) | 8, and TSSOP (PW) | 8 packages). The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-2 through Table 4-13 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality.
BNo device damage, but loss of functionality.
CNo device damage, but performance degradation.
DNo device damage, no impact to functionality or performance.

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • Short Circuit to Power and Short Circuit to Supply mean short to V+
  • Short Circuit to GND and Short Circuit to Ground mean short to V‒
  • V+ is equivalent to VCC
  • V‒ is equivalent to VEE