SFFSBL3 November   2026 TPS22810-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
  7. 5Revision History

Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the TPS22810-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to ground (see Table 4-3)
  • Pin open-circuited (see Table 4-4)
  • Pin short-circuited to an adjacent pin (see Table 4-5)
  • Pin short-circuited to supply (see Table 4-6)

Table 4-3 through Table 4-6 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality.
BNo device damage, but loss of functionality.
CNo device damage, but performance degradation.
DNo device damage, no impact to functionality or performance.

Figure 4-1 shows the TPS22810-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TPS22810-Q1 datasheet.

TPS22810-Q1 Pin DiagramFigure 4-1 Pin Diagram
Table 4-2 Pin Descriptions
PINI/ODESCRIPTION
NO.NAME
1VINISwitch input.
2GND—Device ground.
3EN/UVLOIActive high switch control input and UVLO adjustment. Do not leave floating
4CTOSwitch slew rate control. Can be left floating
5QODOQuick Output Discharge pin. This functionality can be enabled in one of three ways.
  • Placing an external resistor between VOUT and QOD
  • Tying QOD directly to VOUT and using the internal resistor value (RPD)
  • Disabling QOD by leaving pin floating
6VOUTOSwitch output.

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • The absolute maximum ratings for the device are not exceeded.
Table 4-3 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
VIN1The power supply is shorted.B
GND2This is the intended operation for the GND pin.D
EN/UVLO3The device is disabled.B
CT4Grounding this pin prevents the device from turning on.B
QOD5If the QOD pin is left floating in the application, short to ground has no effect. If the QOD pin is connected to the VOUT pin, the device thermally cycles until the short to ground is removed, repetitive cycles can potentially damage the device.A
VOUT6The device thermally cycles until the short to ground is removed, repetitive cycles can potentially damage the device.A
Table 4-4 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
VIN1There is no power supply to the device. The device does not pass through voltage to the VOUT pin.B
GND2There is no GND connection to the device. The device is not functional.B
EN/UVLO3The EN/UVLO pin potentially floats high or low, the output state is unknown.B
CT4The output rise time is no longer controlled; the device turns on at the fastest slew rate of the device with higher inrush current.C
QOD5If the QOD pin is left floating in the application, there is no quick output discharge functionality.B
VOUT6The output does not deliver the voltage to the load.B
Table 4-5 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure EffectsFailure Effect Class
VIN1GNDThe power supply is shorted.B
GND2EN/UVLOThe device is disabled.B
CT4QODIf QOD is tied to VOUT, CT is pulled up to VIN and can potentially damage the device. If QOD is floating, no effect.A
QOD5VOUTThe discharge rate after the switch becomes disabled, and is controlled with the value of the internal pull-down resistance.D
Table 4-6 Pin FMA for Device Pins Short-Circuited to Supply
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
VIN1The device operates normally, as expected.D
GND2The power supply is shorted.B
EN/UVLO3The device is enabled if the power supply is above the EN threshold (VENR).B
CT4Biasing the CT pin can potentially damage the device.A
QOD5Having continuous power on the QOD pin can potentially damage the device.A
VOUT6The switch is bypassed, so the output cannot be turned off. If QOD is tied to VOUT, the device can be damaged.A