SFFSBL3 November 2026 TPS22810-Q1
This section provides a failure mode analysis (FMA) for the pins of the TPS22810-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-3 through Table 4-6 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Figure 4-1 shows the TPS22810-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TPS22810-Q1 datasheet.
Figure 4-1 Pin Diagram| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | VIN | I | Switch input. |
| 2 | GND | — | Device ground. |
| 3 | EN/UVLO | I | Active high switch control input and UVLO adjustment. Do not leave floating |
| 4 | CT | O | Switch slew rate control. Can be left floating |
| 5 | QOD | O | Quick Output Discharge pin. This functionality can be enabled in one of three ways.
|
| 6 | VOUT | O | Switch output. |
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VIN | 1 | The power supply is shorted. | B |
| GND | 2 | This is the intended operation for the GND pin. | D |
| EN/UVLO | 3 | The device is disabled. | B |
| CT | 4 | Grounding this pin prevents the device from turning on. | B |
| QOD | 5 | If the QOD pin is left floating in the application, short to ground has no effect. If the QOD pin is connected to the VOUT pin, the device thermally cycles until the short to ground is removed, repetitive cycles can potentially damage the device. | A |
| VOUT | 6 | The device thermally cycles until the short to ground is removed, repetitive cycles can potentially damage the device. | A |
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VIN | 1 | There is no power supply to the device. The device does not pass through voltage to the VOUT pin. | B |
| GND | 2 | There is no GND connection to the device. The device is not functional. | B |
| EN/UVLO | 3 | The EN/UVLO pin potentially floats high or low, the output state is unknown. | B |
| CT | 4 | The output rise time is no longer controlled; the device turns on at the fastest slew rate of the device with higher inrush current. | C |
| QOD | 5 | If the QOD pin is left floating in the application, there is no quick output discharge functionality. | B |
| VOUT | 6 | The output does not deliver the voltage to the load. | B |
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| VIN | 1 | GND | The power supply is shorted. | B |
| GND | 2 | EN/UVLO | The device is disabled. | B |
| CT | 4 | QOD | If QOD is tied to VOUT, CT is pulled up to VIN and can potentially damage the device. If QOD is floating, no effect. | A |
| QOD | 5 | VOUT | The discharge rate after the switch becomes disabled, and is controlled with the value of the internal pull-down resistance. | D |
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| VIN | 1 | The device operates normally, as expected. | D |
| GND | 2 | The power supply is shorted. | B |
| EN/UVLO | 3 | The device is enabled if the power supply is above the EN threshold (VENR). | B |
| CT | 4 | Biasing the CT pin can potentially damage the device. | A |
| QOD | 5 | Having continuous power on the QOD pin can potentially damage the device. | A |
| VOUT | 6 | The switch is bypassed, so the output cannot be turned off. If QOD is tied to VOUT, the device can be damaged. | A |