SGLS118E December   2001  – July 2024 TPS769-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Dissipation Ratings (Legacy Chip)
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
    8. 5.8 Typical Characteristics: Supported ESR Range
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Output Pulldown
      6. 6.3.6 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Adjustable Device Feedback Resistors
        2. 7.2.2.2 Recommended Capacitor Types
        3. 7.2.2.3 Input and Output Capacitor Requirements
        4. 7.2.2.4 Reverse Current
        5. 7.2.2.5 Feed-Forward Capacitor (CFF)
        6. 7.2.2.6 Power Dissipation (PD)
        7. 7.2.2.7 Estimating Junction Temperature
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Module
        2. 8.1.1.2 Spice Models
        3. 8.1.1.3 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.3 Application Curves

TPS769-Q1 Power-Up Waveform (Legacy Chip)
Channel 1 = VOUT, channel 2 = VIN, channel 4 = IOUT
Figure 7-4 Power-Up Waveform (Legacy Chip)
TPS769-Q1 LDO Start-Up Time With Input supply (New Chip)
 
Figure 7-6 LDO Start-Up Time With Input supply (New Chip)
TPS769-Q1 TPS76915-Q1 Line Transient Response (Legacy Chip)
 
Figure 7-8 TPS76915-Q1 Line Transient Response (Legacy Chip)
TPS769-Q1 TPS76933-Q1 Line Transient Response (Legacy Chip)
 
Figure 7-10 TPS76933-Q1 Line Transient Response (Legacy Chip)
TPS769-Q1 TPS76933-Q1 Line Transient Response (New Chip)
4.3V to 16.0V at 1V/μs
Figure 7-12 TPS76933-Q1 Line Transient Response (New Chip)
TPS769-Q1 TPS76933-Q1 Load Transient Response (New Chip)
1mA to 100mA at 1A/μs
Figure 7-14 TPS76933-Q1 Load Transient Response (New Chip)
TPS769-Q1 TPS76933-Q1 Load Transient Response (New Chip)
1mA to 100mA at 1mA/μs
Figure 7-16 TPS76933-Q1 Load Transient Response (New Chip)
TPS769-Q1 Power-Down Waveform (Legacy Chip)
Channel 1 = VOUT, channel 2 = VIN, channel 4 = IOUT
Figure 7-5 Power-Down Waveform (Legacy Chip)
TPS769-Q1 LDO Start-Up Time With EN (New Chip)
 
Figure 7-7 LDO Start-Up Time With EN (New Chip)
TPS769-Q1 TPS76915-Q1 Load Transient Response (Legacy Chip)
 
Figure 7-9 TPS76915-Q1 Load Transient Response (Legacy Chip)
TPS769-Q1 TPS76933-Q1 Line Transient Response (New Chip)
4.3V to 5.3V at 1V/μs
Figure 7-11 TPS76933-Q1 Line Transient Response (New Chip)
TPS769-Q1 TPS76933-Q1 Load Transient Response (Legacy Chip)
 
Figure 7-13 TPS76933-Q1 Load Transient Response (Legacy Chip)
TPS769-Q1 TPS76933-Q1 Load Transient Response (New Chip)
1μA to 100mA at 1A/μs
Figure 7-15 TPS76933-Q1 Load Transient Response (New Chip)