SGLS390G July   2009  – November 2015 CDCM7005-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Automatic/Manual Reference Clock Switching
      2. 9.3.2 PLL Lock for Analog and Digital Detect
        1. 9.3.2.1 PLL Lock/Out-of-Lock Definition
        2. 9.3.2.2 Digital vs Analog Lock
      3. 9.3.3 Differential LVPECL Outputs and Single-Ended LVCMOS Outputs
      4. 9.3.4 Frequency Hold-Over Mode
      5. 9.3.5 Charge Pump Preset to VCC_CP / 2
      6. 9.3.6 Charge Pump Current Direction
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 SPI Control Interface
      2. 9.5.2 Functional Description of the Logic
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Clock Generation for Interpolating DACs With the CDCM7005-SP
        1. 10.1.1.1 AC-Coupled Interface to ADC/DAC
      2. 10.1.2 Phase Noise Performance
        1. 10.1.2.1 In-Band Noise Performance
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

HFG Package
52-Pin CFP
Top View
CDCM7005-SP hfga_52_gls390.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
VCC 19, 22,
23, 26,
28, 31,
32, 35,
36, 39,
41, 44,
46, 47,
48		 Power 3.3-V supply. VCC and AVCC should always have same supply voltage. It is recommended that AVCC use its own supply filter.
GND Thermal pad, and Pins: 1, 7, 11, 13, 45, 51 Ground Ground
AVCC 3, 6, 9
16, 17		 Analog Power 3.3-V analog power supply. There is no internal connection between AVCC and VCC. It is recommended that AVCC use its own supply filter.
VCC_CP 10 Power This is the charge pump power supply pin used to have the same supply as the external VCO. It can be set from 2.3 V to 3.6 V.
CTRL_LE 5 I LVCMOS input, control latch enable for serial programmable Interface (SPI), with hysteresis. Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCC.
CTRL_CLK 4 I LVCMOS input, serial control clock input for SPI, with hysteresis. Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCC.
CTRL_DATA 2 I LVCMOS input, serial control data input for SPI, with hysteresis. Unused or floating inputs must be tied to proper logic level. It is recommended to use a 20-kΩ or larger pullup resistor to VCC.
PD 27 I LVCMOS input, asynchronous power down (PD) signal. This pin is low active and can be activated external or by the corresponding bit in the SPI register (in case of logic high, the SPI setting is valid). Switches the device into power-down mode. Resets M- and N-Divider, 3-states charge pump, STATUS_REF, or PRI_SEC_CLK pin, STATUS_VCXO or I_REF_CP pin, PLL_LOCK pin, VBB pin and all Yx outputs. Sets the SPI register to default value; has internal 150-kΩ pullup resistor.
It is recommended to ramp up the PD with the same time as VCC and AVCC or later. The ramp up rate of the PD should not be faster than the ramp up rate of VCC and AVCC.
RESET or
HOLD 		40 I This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET is the default function. This pin is low active and can be activated external or via the corresponding bit in the SPI register. In case of RESET, the charge pump (CP) is switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider settings are maintained in SPI registers). The LVPECL outputs are static low and high respectively and the LVCMOS outputs are all low or high if inverted. RESET is not edge triggered and should have a pulse duration of at least 5 ns.
In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is released and with the next valid reference clock cycle the charge pump is switched back in to normal operation (CP stays in 3-state as long as no reference clock is valid). During HOLD, the P divider and all outputs Yx are at normal operation. This mode allows an external control of the frequency hold-over mode.
The input has an internal 150-kΩ pullup resistor.
VCXO_IN 21 I VCXO LVPECL input
VCXO_IN 20 I Complementary VCXO LVPECL input
PRI_REF 14 I LVCMOS input for the primary reference clock, with an internal 150-kΩ pullup resistor and input hysteresis.
SEC_REF 15 I LVCMOS input for the secondary reference clock, with an internal 150-kΩ pullup resistor and input hysteresis.
REF_SEL 12 I LVCMOS reference clock selection input. In the manual mode the REF_SEL signal selects one of the two input clocks:
REF_SEL [1]: PRI_REF is selected;
REF_SEL [0]: SEC_REF is selected;
The input has an internal 150-kΩ pullup resistor.
CP_OUT 8 O Charge pump output
VBB 18 O Bias voltage output to be used to bias unused complementary input VCXO_IN for single ended signals. The output of VBB is VCC – 1.3 V. The output current is limited to about 1.5 mA.
STATUS_REF or
PRI_SEC_CLK		 50 O This output can be programmed (SPI) to provide either the STATUS_REF or PRI_SEC_CLK information. This pin is set high if one of the STATUS conditions is valid. STATUS_REF is the default setting.
In case of STATUS_REF, the LVCMOS output provides the Status of the Reference Clock. If a reference clock with a frequency above 2 MHz is provided to PRI_REF or SEC_REF STATUS_REF will be set high.
In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primary clock [high] or the secondary clock [low] is selected.
STATUS_VCXO
or I_REF_CP		 49 O This LVCMOS output can be programmed (SPI) to provide either the STATUS_VCXO information or serve as current path for the charge pump (CP). STATUS_VCXO is the default setting.
In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO input (frequencies above 2 MHz are interpreted as valid clock; active high).
In case of I_REF_CP, it provides the current path for the external reference resistor
(12 kΩ ±1%) to support an accurate charge pump current, optional. Do not use any capacitor across this resistor to prevent noise coupling via this node. If the internal 12 kΩ is selected (default setting), this pin can be left open.
PLL_LOCK 52 I/O LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in lock (see feature description). This output can be programmed to be digital lock detect or analog lock detect (see feature description).
The PLL is locked (set high), if the rising edge either of PRI_REF or SEC_REF clock and VCXO_IN clock at the phase frequency detector (PFD) are inside the lock detect window for a predetermined number of successive clock cycles.
The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or SEC_REF) clock and VCXO_IN clock at the PFD are outside the lock detect window or if a certain frequency offset between reference frequency and feedback frequency (VCXO) is detected.
Both, the lock detect window and the number of successive clock cycles are user definable (via SPI).
Y0A:Y0B
Y1A:Y1B
Y2A:Y2B
Y3A:Y3B
Y4A:Y4B		 24, 25,
29, 30,
33, 34,
37,38,
42, 43		 O The outputs of the CDCM7005-SP are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The outputs are selectable via SPI (Word 1, Bit 2-6). The power-up setting is all outputs are LVPECL.