SLAA998 May   2021 DAC43701 , DAC43701-Q1 , DAC53701 , DAC53701-Q1

 

  1.   Design Objective
  2.   Design Description
  3.   Design Requirements and Detailed Design Procedure
  4.   Error Calculation and Thermal Management
  5.   Test Setup and Measurements
  6.   Register Settings
  7.   Pseudocode Examples
  8.   Design Featured Devices
  9.   Design References

Design Requirements and Detailed Design Procedure

The design procedure is laid out with the following requirements and components in mind

  • Slew time approximately 1.5s
  • Bright LED current = 20mA
  • Dim LED current = 10mA
  • MOSFET CSD16342Q5A
  • DAC53701 (the DAC43701 is an 8-bit device while the DAC53701 is a 10-bit device. This example uses the latter)

Choose a small VSET so that the power dissipation across RSET is minimum. While there is an option to use the DACx3701 with either an external or an internal reference, it is important to note that the DACx3701 has a single supply voltage which will also serve as a reference in the external mode. In a practical scenario, it is unlikely that a user would have a precision reference available for VDD. With the standard power supplies, the noise and accuracy of an external reference will not be at par with the internal reference of the DACx3701. It is therefore recommended to use the internal reference of the DACx3701 to have an accurate ISET.

A VSET of 1V is chosen for the bright condition. The internal reference of the device is 1.212V with optional gain settings of 1.5×, 2×, 3×, or 4×. Using the 1.5× gain setting, the DAC53701 will have an output span of 1.212 V × 1.5 = 1.818 V (the internal reference of the DAC is trimmed to 1.212V (typical) at room temperature). This results in RSETof 1 V / 20 m A = 50

The output buffer of the DAC is connected in a force-sense configuration to the MOSFET as previously shown. This configuration compensates the gate-source voltage drop caused by temperature, drain current, and aging of the MOSFET. Considering a typical gate-source voltage of 1.2V and a power supply headroom of 200mV, the VDD for the DAC must be a minimum of (1V + 1.2V + 200mV) = 2.4V. Use a standard 3.3-V or 5-V power supply for the DAC. A bipolar junction transistor (BJT) provides a much smaller base-emitter voltage drop, but a MOSFET has better matching between the drain and source currents. It is recommended to choose BJT over the MOSFET when less than 2.4-V supply voltage is available for the DAC. The fact that the power supply of the DAC should be kept at or below 5.5V imposes a constraint on the VGS across the MOSFET for higher values of VSET. The VGS of the MOSFET will change with temperature and with ISET as well. A higher ISET requires a higher VGS but a high VSET may clip the VGS and subsequently the MOSFET current due to the supply limitations of the DAC. This presents a stronger case to use a lower VSET.

Configure the MARGIN-HIGH register value to the code equivalent of 1V; that is ( 1 V 1.818 V ) × 1024 = 563 d or 0x233. The MARGIN-LOW value should be the equivalent of the dim LED current that is 10mA, which corresponds to a DAC voltage of ( 10 m A × 50 ) = 500 m V . The code for MARGIN-LOW is ( 500 m V 1.818 V ) × 1024 = 282 d or 0x11A.