SLAAEO3 September 2024 MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1
Table 2-1 describes the LCD module features that are available on MSPM0 MCUs.
| Parameter | LCD |
|---|---|
| Number of segments supported(1) | 408/8-mux |
| Mux mode supported | 8, 7, 6, 5, 4, 3, 2, Static |
| Segment functionality against port pin selection | Individual selection |
| Flexible configuration for COM and Segment pins | YES |
| LCD clock selection | LFCLK |
| LCD clock divider availability | 1 to 32 |
| Interrupt capabilities | YES (3 sources) |
| Whole display blinking | YES |
| Programmable blinking frequency | YES |
| Individual segment blinking capabilities with separate memory | Yes (Static and 2-4 Mux mode) |
| Dual memory display | YES |
| Bias mode | Static, 1/3 and 1/4 |
| LCD bias generation using resistive network | External or Internal |
| Device protection against no connected capacitance on LOADCAP when charge pump is used | NO need for protection (A 0.1µF or larger capacitor must be connected from LOADCAP0 and LOADCAP1 pins) |
| Charge pump voltage with external voltage reference | 3 or 4 × Vref depends on bias mode |
| Low-power waveforms mode | YES |