SLASEW9E February   2023  – October 2025 MSPM0G1505 , MSPM0G1506 , MSPM0G1507

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
        1. 7.6.1.1 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 SYSOSC Typical Frequency Accuracy
        1. 7.9.2.1 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
    13. 7.13 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Voltage Characteristics
      2. 7.15.2 Electrical Characteristics
    16. 7.16 Comparator (COMP)
      1. 7.16.1 Comparator Electrical Characteristics
    17. 7.17 DAC
      1. 7.17.1 DAC_Supply Specifications
      2. 7.17.2 DAC Output Specifications
      3. 7.17.3 DAC Dynamic Specifications
      4. 7.17.4 DAC Linearity Specifications
      5. 7.17.5 DAC Timing Specifications
    18. 7.18 GPAMP
      1. 7.18.1 Electrical Characteristics
      2. 7.18.2 Switching Characteristics
    19. 7.19 OPA
      1. 7.19.1 Electrical Characteristics
      2. 7.19.2 Switching Characteristics
      3. 7.19.3 PGA Mode
    20. 7.20 I2C
      1. 7.20.1 I2C Characteristics
      2. 7.20.2 I2C Filter
        1. 7.20.2.1 I2C Timing Diagram
    21. 7.21 SPI
      1. 7.21.1 SPI
      2. 7.21.2 SPI Timing Diagram
    22. 7.22 UART
    23. 7.23 TIMx
    24. 7.24 TRNG
      1. 7.24.1 TRNG Electrical Characteristics
      2. 7.24.2 TRNG Switching Characteristics
    25. 7.25 Emulation and Debug
      1. 7.25.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G150x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 COMP
    16. 8.16 DAC
    17. 8.17 OPA
    18. 8.18 GPAMP
    19. 8.19 TRNG
    20. 8.20 AES
    21. 8.21 CRC
    22. 8.22 UART
    23. 8.23 I2C
    24. 8.24 SPI
    25. 8.25 WWDT
    26. 8.26 RTC
    27. 8.27 Timers (TIMx)
    28. 8.28 Device Analog Connections
    29. 8.29 Input/Output Diagrams
    30. 8.30 Serial Wire Debug Interface
    31. 8.31 Bootstrap Loader (BSL)
    32. 8.32 Device Factory Constants
    33. 8.33 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

11 Revision History

Changes from March 1, 2025 to October 3, 2025 (from Revision D (March 2025) to Revision E (October 2025))

  • Added comlementary output to the advanced timer feature descriptionGo
  • Added WWDT acronym to the windowed watch dog timer feature descriptionGo
  • Added pitch and package identifier details to package options listGo
  • Changed communications feature section formatting for clarityGo
  • Added "open drain" to 5V IO descriptionGo
  • Added "GPAMP" to list of analog peripherals with internal connectionsGo
  • Added number of high speed IOs to Flexible I/O Features sectionGo
  • Updated Optimized Low-Power Mode sectionGo
  • Removed functional safety branding from industrial variant datasheetGo
  • Updated device comparison information for YCJ packagesGo
  • Changed VSSOP width from 3mm to 4.9mm to account for leadsGo
  • Added package pitch informationGo
  • Removed wildcard from part numberGo
  • Updated comparison table valuesGo
  • Added "R" to OPNs to designate distribution formatGo
  • Added DSBGA package pin attributesGo
  • Moved Digital Features by IO Type to beginning of Pin Attributes sectionGo
  • Added WCSP package signal descriptionsGo
  • Added pin type information to the beginning of the Signal Description sectionGo
  • Added footnote to absolute maximum ratings section for diode current injection limitation on PA21 GPIO pinGo
  • Added I_VDD/I_VSS missing footnote to absolute maximum ratings for lower current at VDD=1.62VGo
  • Updated LFOSC start-up time specification from 1.7ms to 1ms Go
  • Updated Digital IO VOL specification for HSIO to correctly reference temperature condition to match with other IO types for this specGo
  • Updated Digital IO Electrical specifications and Switching specifications sections with added footnote for series current limiting resistor when using HDIO in DRV=1 drive strength settingGo
  • Added Digital IO switching specifications line item for port output frequency for HDIO operation with DRV=1 drive strength settingGo
  • Added condition for comparator electrical specifications section on I_comp specification HCYCLE register settingGo
  • Updated power-on reset voltage level specificationsGo
  • Updated BOR COLD specification sectionGo
  • Changed the VBOR0- falling from 1.56 to 1.55Go
  • Added SLEEP0 wakeup timeGo
  • Changed "fSYSOSC additional undershoot accuracy during tsettle" min from -11 to -16Go
  • Changed SYSPLLCLK0/1from 1MHz to 2.5MHzGo
  • Changed SYSPLLCLK0/1from 1MHz to 2.5MHzGo
  • Changed SYSPLL RMS cycle-to-cycle jitter from 24ps to 60psGo
  • Changed period jitter from 15.5ps to 45psGo
  • Changed the SYSPLL typical start up time from 14us to 7us, and the maximum start up time from 24us to 18usGo
  • Changed VDD ≥ 2.7V, DRV = 1, CL= 20pF specification from 40MHz to 32MHzGo
  • 32Changed VDD ≥ 2.7V, DRV = 1, CL= 20pF specification from 40MHz to 32MHzGo
  • Changed I_VBST from 0.7uA to 0.8uAGo
  • Changed ADC operating current from 1.5mA to 1.75mAGo
  • Added "f_in = 10KHz" test conditionGo
  • Changed V_SupplyMon max from 1% to 1.5%Go
  • Changed offset error from +/-2mV to +/-3.5mVGo
  • Changed gain error from +/-3LSB to +/-4LSBGo
  • Changed temperature sensor settling time from 10us to 12.5usGo
  • Added COMP + VREF current consumption in low power modeGo
  • Changed COMP low power mode current consumption from 0.84uA to 0.85uAGo
  • Changed COMP IDD from 102uA to 120uAGo
  • Split parameter section of comparator current consumption sectionGo
  • Changed COMP+VREF low power mode IDD spec from 2.5uA to 3.5uAGo
  • Added DAC code test conditionGo
  • Changed DAC IDD from 300uA to 400uAGo
  • Added V_o = 0.3V to VDD-0.3V test conditionGo
  • Removed +/- from output load current and only made it +4mA.Go
  • Changed non- inverting gain error (Gain=32) from (-2.6% to +2.6%) to (-3.2% to +2%)Go
  • Changed inverting gain error (Gain=-31) from (-2.7% to +2.7%) to (-3.3% to +2.1%)Go
  • Changed the temperature sensor calibration condition from 1.4V to 3.3V with the correct register configuration settingGo
  • Added block diagram of VREF moduleGo