SLASF36A January   2024  – December 2024 TAC5311-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI Interface
    9. 5.9  Switching Characteristics: SPI Interface
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Charactaristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3  Input Channel Configuration
      4. 6.3.4  Reference Voltage
      5. 6.3.5  Microphone Bias
      6. 6.3.6  Digital PDM Microphone Record Channel
      7. 6.3.7  Signal-Chain Processing
        1. 6.3.7.1 ADC Signal-Chain
          1. 6.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.1.2 Programmable Channel Gain Calibration
          3. 6.3.7.1.3 Programmable Channel Phase Calibration
          4. 6.3.7.1.4 Programmable Digital High-Pass Filter
          5. 6.3.7.1.5 Programmable Digital Biquad Filters
          6. 6.3.7.1.6 Programmable Channel Summer and Digital Mixer
          7. 6.3.7.1.7 Configurable Digital Decimation Filters
            1. 6.3.7.1.7.1 Linear-phase filters
              1. 6.3.7.1.7.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.7.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.7.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.7.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.7.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.7.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.7.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.7.1.7.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.7.1.7.1.9 Sampling Rate: 768kHz or 705.6kHz
            2. 6.3.7.1.7.2 Low-latency Filters
              1. 6.3.7.1.7.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.7.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.7.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.7.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.7.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.7.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.7.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.7.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.7.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.7.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.7.3.5 Sampling Rate: 192kHz or 176.4kHz
        2. 6.3.7.2 DAC Signal-Chain
          1. 6.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.2.2 Programmable Channel Gain Calibration
          3. 6.3.7.2.3 Programmable Digital High-Pass Filter
          4. 6.3.7.2.4 Programmable Digital Biquad Filters
          5. 6.3.7.2.5 Programmable Digital Mixer
          6. 6.3.7.2.6 Configurable Digital Interpolation Filters
            1. 6.3.7.2.6.1 Linear-phase filters
              1. 6.3.7.2.6.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.2.6.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.2.6.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.2.6.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.2.6.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.2.6.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.2.6.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.7.2.6.2 Low-latency Filters
              1. 6.3.7.2.6.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.6.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.6.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.6.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.6.2.5 Sampling Rate: 192kHz or 176.4kHz
      8. 6.3.8  Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9  Input DC Fault Diagnostics
      10. 6.3.10 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Software Reset
      3. 6.4.3 Active Mode
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAC5311-Q1_B0_P0 Registers
      2. 7.1.2 TAC5311-Q1_B0_P1 Registers
    2. 7.2 Programmable Coefficienct Registers
      1. 7.2.1  Programmable Coefficient Registers: Page 8
      2. 7.2.2  Programmable Coefficient Registers: Page 9
        1. 7.2.2.1 TAC5311-Q1_B0_P3 Registers
      3. 7.2.3  Programmable Coefficient Registers: Page 10
      4. 7.2.4  Programmable Coefficient Registers: Page 11
      5. 7.2.5  Programmable Coefficient Registers: Page 15
      6. 7.2.6  Programmable Coefficient Registers: Page 16
      7. 7.2.7  Programmable Coefficient Registers: Page 17
      8. 7.2.8  Programmable Coefficient Registers: Page 18
      9. 7.2.9  Programmable Coefficient Registers: Page 19
      10. 7.2.10 Programmable Coefficient Registers: Page 25
      11. 7.2.11 Programmable Coefficient Registers: Page 26
      12. 7.2.12 Programmable Coefficient Registers: Page 27
      13. 7.2.13 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Example Device Register Configuration Scripts for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.5 Example Device Register Configuration Scripts for EVM Setup

This section provides a typical EVM I2C register control script for various applications.

Mono differential analog AC-coupled input recording and line output playback

# Key: w a0 XX YY ==> write to I2C address 0xa0, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
#
# Differential 1-channel ADC: INP1/INM1 - Ch1
# Differential 1-channel Line Out DAC: OUT1P/OUT1M - Ch1
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 12.288 MHz (BCLK/FSYNC = 256)
# AVDD = 3.3 V; IOVDD = 3.3 V; BSTVDD = 3.3 V
################################################################
#
#

# Page 0 Register Writes
w a0 00 00
w a0 01 01	#SW Reset
d 01

#Page 1 Register Writes
w a0 00 01
w a0 73 B0 #MICBIAS set to 8V

# Page 0 Register Writes
w a0 00 00
w a0 02 09	#Exit Sleep Mode with DREG and VREF Enabled

w a0 1a 30	#TDM protocol with 32-bit word length

w a0 50 00	#ADC Channel 1 configured for AC-coupled differential input with 10Vrms swing and audio bandwidth

w a0 64 20	#DAC Channel 1 configured for differential output with 0.6*Vref as common mode
w a0 65 20	#DAC OUT1P configured for line out driver and audio bandwidth
w a0 66 20	#DAC OUT1M configured for line out driver and audio bandwidth

w a0 76 88	#Input Channel 1 enabled; Output Channel 1 enabled

w a0 78 e0	#ADC, DAC Powered Up

# Apply FSYNC = 48 kHz and BCLK = 12.288 MHz and
# Start recording/playback data by host on ASI bus with TDM protocol 32-bits channel wordlength

Mono differential analog DC-coupled input recording and line output playback

# Key: w a0 XX YY ==> write to I2C address 0xa0, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
#
# Differential 1-channel ADC: INP1/INM1 - Ch1
# Differential 1-channel Line Out DAC: OUT1P/OUT1M - Ch1
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 12.288 MHz (BCLK/FSYNC = 256)
# AVDD = 3.3 V; IOVDD = 3.3 V; BSTVDD = 3.3 V
################################################################
#
#

# Page 0 Register Writes
w a0 00 00
w a0 01 01	#SW Reset
d 01

#Page 1 Register Writes
w a0 00 01
w a0 73 B0 #MICBIAS set to 8V

# Page 0 Register Writes
w a0 00 00
w a0 02 09	#Exit Sleep Mode with DREG and VREF Enabled

w a0 1a 30	#TDM protocol with 32-bit word length

w a0 50 08	#ADC Channel 1 configured for DC-coupled differential input with 10Vrms swing and audio bandwidth

w a0 64 20	#DAC Channel 1 configured for differential output with 0.6*Vref as common mode
w a0 65 20	#DAC OUT1P configured for line out driver and audio bandwidth
w a0 66 20	#DAC OUT1M configured for line out driver and audio bandwidth

w a0 76 88	#Input Channel 1 enabled; Output Channel 1 enabled

w a0 78 e0	#ADC, DAC Powered Up

# Apply FSYNC = 48 kHz and BCLK = 12.288 MHz and
# Start recording/playback data by host on ASI bus with TDM protocol 32-bits channel wordlength

Four-channel PDM microphone recording

# Key: w a0 XX YY ==> write to I2C address 0xa0, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
#
# GPIO1 - PDMCLK @ 3.072MHz
# PDM Ch1/2 on GPIO2
# PDM Ch3/4 on GPI1
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 12.288 MHz (BCLK/FSYNC = 256)
# AVDD = 3.3 V; IOVDD = 3.3 V
################################################################
#
#

# Page 0 Register Writes
w a0 00 00
w a0 01 01	#SW Reset


# Page 0 Register Writes
w a0 00 00
w a0 02 09	#Exit Sleep Mode with DREG and VREF Enabled

w a0 0a 41	#Configure GPIO1 as PDMCLK, with active high/active low drive
w a0 35 00	#PDMCLK frequency = 3.072 MHz

w a0 0d 03	#Configre GPI1A and GPI2A as GPI input

w a0 13 cb	#Configure Channel1 and Channel2 as PDM; PDM1/2 data in on GPI2A; PDM3/4 data in on GPI1A

w a0 1a 30	#TDM protocol with 32-bit word length

w a0 1e 20	#Channel1 data on TDM slot 0
w a0 1f 21	#Channel2 data on TDM slot 1
w a0 20 22	#Channel3 data on TDM slot 2
w a0 21 23	#Channel4 data on TDM slot 3

w a0 76 f0	#Enable input channels 1-4

w a0 78 80	#Power Up ADC path


# Provide BCLK, FSYNC corresponding to 48kSPS, and record with 32-bit TDM bus