SLASFC1A December   2023  – January 2025 TAD5212

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI Interface
    9. 5.9  Switching Characteristics: SPI Interface
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3 Output Channel Configurations
      4. 6.3.4 Reference Voltage
      5. 6.3.5 Programmable Microphone Bias
      6. 6.3.6 Digital PDM Microphone Record Channel
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 DAC Signal-Chain
          1. 6.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.1.2 Programmable Channel Gain Calibration
          3. 6.3.7.1.3 Programmable Digital High-Pass Filter
          4. 6.3.7.1.4 Programmable Digital Biquad Filters
          5. 6.3.7.1.5 Configurable Digital Interpolation Filters
            1. 6.3.7.1.5.1 Linear-phase filters
              1. 6.3.7.1.5.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.5.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.5.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.5.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.5.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.5.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.5.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.7.1.5.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.7.1.5.1.9 Sampling Rate 768kHz or 705.6kHz
            2. 6.3.7.1.5.2 Low-latency Filters
              1. 6.3.7.1.5.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.5.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.5.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.5.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.5.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.5.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.5.3.1 Sampling Rate: 24 kHz or 22.05 kHz
              2. 6.3.7.1.5.3.2 Sampling Rate: 32 kHz or 29.4 kHz
              3. 6.3.7.1.5.3.3 Sampling Rate: 48 kHz or 44.1 kHz
              4. 6.3.7.1.5.3.4 Sampling Rate: 96 kHz or 88.2 kHz
              5. 6.3.7.1.5.3.5 Sampling Rate 192 kHz or 176.4 kHz
          6. 6.3.7.1.6 Programmable Digital Mixer
        2. 6.3.7.2 PDM Recording Signal-Chain
          1. 6.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.2.2 Programmable Channel Gain Calibration
          3. 6.3.7.2.3 Programmable Channel Phase Calibration
          4. 6.3.7.2.4 Programmable Digital High-Pass Filter
          5. 6.3.7.2.5 Programmable Digital Biquad Filters
          6. 6.3.7.2.6 Configurable Digital Decimation Filters
            1. 6.3.7.2.6.1 Linear-phase filters
              1. 6.3.7.2.6.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.2.6.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.2.6.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.2.6.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.2.6.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.2.6.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.2.6.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.7.2.6.2 Low-latency Filters
              1. 6.3.7.2.6.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.6.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.6.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.6.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.6.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.2.6.3 Ultra Low-latency Filters
              1. 6.3.7.2.6.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.6.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.6.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.6.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.6.3.5 Sampling Rate: 192kHz or 176.4kHz
          7. 6.3.7.2.7 Automatic Gain Controller (AGC)
          8. 6.3.7.2.8 Voice Activity Detection (VAD)
          9. 6.3.7.2.9 Ultrasonic Activity Detection (UAD)
      8. 6.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAD5212_B0_P0 Registers
      2. 7.1.2 TAD5212_B0_P1 Registers
      3. 7.1.3 TAD5212_B0_P3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1  Programmable Coefficient Registers: Page 8
      2. 7.2.2  Programmable Coefficient Registers: Page 9
      3. 7.2.3  Programmable Coefficient Registers: Page 10
      4. 7.2.4  Programmable Coefficient Registers: Page 11
      5. 7.2.5  Programmable Coefficient Registers: Page 15
      6. 7.2.6  Programmable Coefficient Registers: Page 16
      7. 7.2.7  Programmable Coefficient Registers: Page 17
      8. 7.2.8  Programmable Coefficient Registers: Page 18
      9. 7.2.9  Programmable Coefficient Registers: Page 19
      10. 7.2.10 Programmable Coefficient Registers: Page 25
      11. 7.2.11 Programmable Coefficient Registers: Page 26
      12. 7.2.12 Programmable Coefficient Registers: Page 27
      13. 7.2.13 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Example Device Register Configuration Script for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD_MODE for 1.8V Operation
      2. 8.3.2 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.3 Detailed Design Procedure

This section describes the necessary steps to configure the TAD5212 for this specific application. The following steps provide a sequence of items that must be executed in the time between powering the device up and reading data from the device or transitioning from one mode to another mode of operation.

  1. Apply power to the device:
    1. Power up the IOVDD and AVDD power supplies
    2. Wait for at least 2ms to allow the device to initialize the internal registers.
    3. The device now goes into sleep mode (low-power mode < 10µA)
  2. Transition from sleep mode to active mode whenever required for the operation:
    1. Wake up the device by writing to P0_R2 to disable sleep mode
    2. Wait for at least 2ms to allow the device to complete the internal wake-up sequence
    3. Override the default configuration registers or programmable coefficients value as required (this step is optional)
    4. Enable all desired audio serial interface input/output channels by writing to P0_R40 to P0_R47 for DAC
    5. Power-up the DAC by writing to P0_R120
    6. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio

      This specific step can be done at any point in the sequence after step a.

      See the Section 6.3.2 section for supported sample rates and the BCLK to FSYNC ratio.

    7. The device playback data is now received from the host processor using the TDM audio serial data bus and this playback data from TDM is now played on the line-out
  3. Transition from active mode to sleep mode (again) as required in the system for low-power operation:
    1. Enter sleep mode by writing to P0_R2 to enable sleep mode
    2. Wait at least 10ms (when FSYNC = 48kHz) for the volume to ramp down and for all blocks to power down
    3. Read P0_R122 to check the device shutdown and sleep mode status
    4. If the device P0_R122_D[7:5] status bit is 3'b100 then stop FSYNC and BCLK in the system
    5. The device now goes into sleep mode (low-power mode < 10µA) and retains all register values
  4. Transition from sleep mode to active mode (again) as required for the recording operation:
    1. Wake up the device by writing to P0_R2 to disable sleep mode
    2. Wait at least 2ms to allow the device to complete the internal wake-up sequence
    3. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
    4. The device playback data is now received from the host processor using the TDM audio serial data bus and this playback data from TDM is now played on the line-out
  5. Repeat the steps as required for different device configurations and modes of operation