SLAZ247Z October   2012  – May 2021 MSP430F5132

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      DA38
      2.      RSB40
      3.      YFF40
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC42
    3. 6.3  ADC69
    4. 6.4  BSL7
    5. 6.5  COMP10
    6. 6.6  CPU21
    7. 6.7  CPU22
    8. 6.8  CPU40
    9. 6.9  CPU46
    10. 6.10 CPU47
    11. 6.11 DMA4
    12. 6.12 DMA7
    13. 6.13 DMA10
    14. 6.14 EEM11
    15. 6.15 EEM17
    16. 6.16 EEM19
    17. 6.17 EEM21
    18. 6.18 EEM23
    19. 6.19 JTAG26
    20. 6.20 JTAG27
    21. 6.21 PMAP1
    22. 6.22 PMM14
    23. 6.23 PMM15
    24. 6.24 PMM18
    25. 6.25 PMM20
    26. 6.26 PMM26
    27. 6.27 PORT15
    28. 6.28 PORT19
    29. 6.29 PORT21
    30. 6.30 SYS12
    31. 6.31 SYS16
    32. 6.32 TD1
    33. 6.33 TD2
    34. 6.34 UCS9
    35. 6.35 UCS11
    36. 6.36 USCI26
    37. 6.37 USCI31
    38. 6.38 USCI34
    39. 6.39 USCI35
    40. 6.40 USCI39
    41. 6.41 USCI40
  7. 7Revision History

6.39 USCI35

USCI Module

Category

Functional

Function

Violation of setup and hold times for (repeated) start in I2C master mode

Description

In I2C master mode, the setup and hold times for a (repeated) START, tSU,STA and tHD,STA respectively, can be violated if SCL clock frequency is greater than 50kHz in standard mode (100kbps). As a result, a slave can receive incorrect data or the I2C bus can be stalled due to clock stretching by the slave.

Workaround

If using repeated start, ensure SCL clock frequencies is < 50kHz in I2C standard mode (100 kbps).