SLAZ298AC October   2012  – August 2021 MSP430F5507

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
    1.     6
    2.     7
      1.      8
    3.     9
  6.   10
    1.     11
    2.     12
    3.     13
    4.     14
    5.     15
    6.     16
    7.     17
    8.     18
    9.     19
    10.     20
    11.     21
    12.     22
    13.     23
    14.     24
    15.     25
    16.     26
    17.     27
    18.     28
    19.     29
    20.     30
    21.     31
    22.     32
    23.     33
    24.     34
    25.     35
    26.     36
    27.     37
    28.     38
    29.     39
    30.     40
    31.     41
    32.     42
    33.     43
    34.     44
    35.     45
    36.     46
    37.     47
    38.     48
    39.     49
    40.     50
    41.     51
    42.     52
    43.     53
    44.     54
    45.     55
    46.     56
    47.     57
    48.     58
    49.     59
    50.     60
    51.     61
    52.     62
    53.     63
    54.     64
    55.     65
    56.     66
    57.     67
    58.     68
    59.     69
    60.     70
    61.     71
    62.     72
    63.     73
    64.     74
    65.     75
    66.     76
  7.   77

6.5 ADC69

ADC Module

Category

Functional

Function

ADC stops operating if ADC clock source is changed from SMCLK to another source while SMCLKOFF = 1.

Description

When SMCLK is used as the clock source for the ADC (ADC12CTL1.ADC12SSELx = 11) and CSCTL4.SMCLKOFF = 1, the ADC will stop operating if the ADC clock source is changed by user software (e.g. in the ISR) from SMCLK to a different clock source. This issue appears only for the ADC12CTL1.ADC12DIVx settings /3/5/7. The hang state can be recovered by PUC/POR/BOR/Power cycle.

Workaround

1. Set CSCTL4.SMCLKOFF = 0 before switch ADC clock source.

OR

2. Only use ADC12CTL1.ADC12DIVx as /1, /2, /4, /6, /8