SLAZ304AC October   2012  – May 2021 MSP430F5515

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PN80
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  BSL6
    2. 6.2  BSL7
    3. 6.3  COMP10
    4. 6.4  CPU21
    5. 6.5  CPU22
    6. 6.6  CPU23
    7. 6.7  CPU26
    8. 6.8  CPU27
    9. 6.9  CPU28
    10. 6.10 CPU29
    11. 6.11 CPU30
    12. 6.12 CPU31
    13. 6.13 CPU32
    14. 6.14 CPU33
    15. 6.15 CPU34
    16. 6.16 CPU35
    17. 6.17 CPU37
    18. 6.18 CPU39
    19. 6.19 CPU40
    20. 6.20 CPU47
    21. 6.21 DMA4
    22. 6.22 DMA7
    23. 6.23 DMA8
    24. 6.24 DMA10
    25. 6.25 EEM9
    26. 6.26 EEM11
    27. 6.27 EEM13
    28. 6.28 EEM14
    29. 6.29 EEM15
    30. 6.30 EEM16
    31. 6.31 EEM17
    32. 6.32 EEM19
    33. 6.33 EEM21
    34. 6.34 EEM23
    35. 6.35 FLASH33
    36. 6.36 FLASH34
    37. 6.37 FLASH35
    38. 6.38 FLASH37
    39. 6.39 JTAG20
    40. 6.40 JTAG26
    41. 6.41 JTAG27
    42. 6.42 MPY1
    43. 6.43 PMAP1
    44. 6.44 PMM9
    45. 6.45 PMM10
    46. 6.46 PMM11
    47. 6.47 PMM12
    48. 6.48 PMM14
    49. 6.49 PMM15
    50. 6.50 PMM17
    51. 6.51 PMM18
    52. 6.52 PMM20
    53. 6.53 PORT15
    54. 6.54 PORT16
    55. 6.55 PORT19
    56. 6.56 PORT24
    57. 6.57 RTC3
    58. 6.58 RTC6
    59. 6.59 SYS10
    60. 6.60 SYS12
    61. 6.61 SYS14
    62. 6.62 SYS16
    63. 6.63 SYS18
    64. 6.64 TAB23
    65. 6.65 USB4
    66. 6.66 USB6
    67. 6.67 USB8
    68. 6.68 USB9
    69. 6.69 USB10
    70. 6.70 USB11
    71. 6.71 USB12
    72. 6.72 USB13
    73. 6.73 USCI26
    74. 6.74 USCI30
    75. 6.75 USCI31
    76. 6.76 USCI34
    77. 6.77 USCI35
    78. 6.78 USCI39
    79. 6.79 USCI40
    80. 6.80 WDG4
  7. 7Revision History

USB6

USB Module

Category

Functional

Function

Endpoint0 STALL bit can be cleared during USBIEPCNFG_0/ USBOEPCNFG_0 register access

Description

According to the MSP430F5xx Family User's Guide (SLAU208), the STALL bit in the Endpoint0 configuration register should be set by software when there is either an unsupported control request or a control request fail or an endpoint halt, and this bit is automatically cleared by the next setup transaction. In correct operation, the hardware clearing of the Endpoint0 STALL bit should not occur when the configuration registers USBIEPCNFG_0/USBOEPCNFG_0 are being accessed even though the next set-up transaction required to clear the STALL bit has occurred. Rather, the hardware clear of the STALL bit should wait until the access is finished, and then clear the bit.  

However due to the erratum, if the next setup transaction occurs while the USBIEPCNFG_0/USBOEPCNFG_0 registers are being accessed, the STALL bit will be cleared immediately.  This can be a problem during write accesses; for example, if the application tries to set the STALL bit and the next set-up transaction has cleared it. In this case, a valid STALL condition might be missed.

Workaround

- Set the STALL bit inside the SETUP ISR. The STALL bit is automatically cleared on entering SETUP ISR so the user does not need to check it is cleared before setting STALL = 1.

or

- Poll the STALL bit to verify it is cleared, then set STALL = 1.

NOTE: The USB stacks supplied by TI implement the first software workaround.