SLAZ547T July   2013  – May 2021 MSP430F5247

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      YFF64
      2.      ZQE80
      3.      RGC64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC42
    3. 6.3  ADC69
    4. 6.4  BSL7
    5. 6.5  COMP10
    6. 6.6  CPU21
    7. 6.7  CPU22
    8. 6.8  CPU40
    9. 6.9  CPU47
    10. 6.10 DMA4
    11. 6.11 DMA7
    12. 6.12 DMA10
    13. 6.13 EEM17
    14. 6.14 EEM19
    15. 6.15 EEM21
    16. 6.16 EEM23
    17. 6.17 JTAG26
    18. 6.18 JTAG27
    19. 6.19 PMAP1
    20. 6.20 PMM9
    21. 6.21 PMM11
    22. 6.22 PMM12
    23. 6.23 PMM14
    24. 6.24 PMM15
    25. 6.25 PMM18
    26. 6.26 PMM20
    27. 6.27 PORT15
    28. 6.28 PORT19
    29. 6.29 PORT33
    30. 6.30 RTC3
    31. 6.31 RTC6
    32. 6.32 SYS12
    33. 6.33 SYS16
    34. 6.34 UCS7
    35. 6.35 UCS9
    36. 6.36 UCS11
    37. 6.37 USCI26
    38. 6.38 USCI34
    39. 6.39 USCI35
    40. 6.40 USCI39
    41. 6.41 USCI40
  7. 7Revision History

UCS7

UCS Module

Category

Functional

Function

DCO drifts when servicing short ISRs when in LPM0 or exiting active from ISRs for short periods of time

Description

The FLL uses two rising edges of the reference clock to compare against the DCO frequency and decide on the required modifications to the DCOx and MODx bits. If the device is in a low power mode with FLL disabled (LPM0 with DCO not sourcing ACLK/SMCLK or LPM2, LPM3, LPM4 where SCG1 bit is set) and enters a state which enables FLL (enter ISR from LPM0/LPM2 or exit active from ISRs) for a period less than 3x reference clock cycles, then the FLL will cause the DCO to drift.
This occurs because the FLL immediately begins comparing an active DCO with its reference clock and making the respective modifications to the DCOx and MODx bits. If the FLL is not given sufficient time to capture a full reference clock cycle (2 x reference clock periods) and adjust accordingly (1 x reference clock period), then the DCO will keep drifting each time the FLL is enabled.

Workaround

(1) If DCO is not sourcing ACLK or SMCLK in the application, use LPM1 instead of LPM0 to make sure FLL is disabled when interrupt service routine is serviced.
(2) When exiting active from ISRs, insert a delay of at least 3 x reference clock periods. To save on power budget, the 3 x reference clock periods could also be spent in LPM0 with TimerA or TimerB using ACLK/SMCLK sourced from DCO. This way, the FLL and DCO are still active in LPM0.