SLAZ668P May   2015  – August 2021 MSP430FG6625

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
    1.     6
    2.     7
      1.      8
      2.      9
      3.      10
    3.     11
  6.   12
    1.     13
    2.     14
    3.     15
    4.     16
    5.     17
    6.     18
    7.     19
    8.     20
    9.     21
    10.     22
    11.     23
    12.     24
    13.     25
    14.     26
    15.     27
    16.     28
    17.     29
    18.     30
    19.     31
    20.     32
    21.     33
    22.     34
    23.     35
    24.     36
    25.     37
    26.     38
    27.     39
    28.     40
    29.     41
    30.     42
    31.     43
    32.     44
    33.     45
    34.     46
    35.     47
  7.   48

PMM14

PMM Module

Category

Functional

Function

Increasing the core level when SVS/SVM low side is configured in full-performance mode causes device reset

Description

When the SVS/SVM low side is configured in full performance mode (SVSMLCTL.SVSLFP = 1), the setting time delay for the SVS comparators is ~2us. When increasing the core level in full-performance mode; the core voltage does not settle to the new level before the settling time delay of the SVS/SVM comparator expires. This results in a device reset.

Workaround

When increasing the core level; enable the SVS/SVM low side in normal mode (SVSMLCTL.SVSLFP=0). This provides a settling time delay of approximately 150us allowing the core sufficient time to increase to the expected voltage before the delay expires.