SLDS237B January   2018  – January  2020 TPS92612-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Typical Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Bias
        1. 7.3.1.1 Power-On Reset (POR)
      2. 7.3.2 Constant-Current Driver
      3. 7.3.3 PWM Dimming
      4. 7.3.4 Protection
        1. 7.3.4.1 Short-to-GND Protection
        2. 7.3.4.2 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Undervoltage Lockout, V(SUPPLY)< V(POR_rising)
      2. 7.4.2 Normal Operation, V(SUPPLY) ≥ 4.5 V
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Single-Channel LED Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Single-Channel LED Driver With Heat Sharing
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6.6 Timing Requirements

MIN NOM MAX UNIT
t(PWM_delay_rising) PWM rising edge delay, 50% PWM voltage to 10% of output current, t2 – t1 as shown in Figure 1 17 µs
t(PWM_delay_falling) PWM falling edge delay, 50% PWM voltage to 90% of output current, t5 – t4 as shown in Figure 1 21 µs
t(TSD_deg) Thermal overtemperature deglitch time 60 µs
t(SG_deg) Channel-output short-to-ground detection deglitch time 80 125 175 µs
t(Recover_deg) Recovery deglitch time 16 µs
TPS92612-Q1 PWM-dimming-measurment-SLDS233.gifFigure 1. Output Timing Diagram