SLLA578 June   2022 TLIN1431-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Startup
    1. 1.1 Operational Voltages
    2. 1.2 Power-Up and INIT Mode
  4. 2Pin Control
    1. 2.1 Typical Application
    2. 2.2 Power-Up into Normal Mode in Pin Control
      1. 2.2.1 Restart Mode from INIT Mode in Pin Control
      2. 2.2.2 Standby Mode from Restart Mode in Pin Control
      3. 2.2.3 Normal Mode in Pin Control
    3. 2.3 Power-Up into Fast Mode in Pin Control
    4. 2.4 Sleep Mode to Normal Mode in Pin Control
    5. 2.5 Fail-Safe Mode to Normal Mode in Pin Control
  5. 3SPI Control
    1. 3.1 Typical Application
    2. 3.2 Power-Up into Normal Mode in SPI Control
      1. 3.2.1 Restart Mode from INIT Mode in SPI Control
      2. 3.2.2 Standby Mode from Restart Mode in SPI Control
      3. 3.2.3 Normal Mode in SPI Control
    3. 3.3 Power-Up into Fast Mode in SPI Control
    4. 3.4 Sleep Mode to Normal Mode in SPI Control
    5. 3.5 Fail-Safe Mode to Normal Mode in SPI Control
    6. 3.6 Configuring Watchdog through SPI
  6. 4Pin Assignments in Pin Control vs. SPI Control
  7. 5References

3.5 Fail-Safe Mode to Normal Mode in SPI Control

Figure 3-8 Fail-Safe Mode in SPI Control

Fail-safe mode can be disabled through a SPI write by setting the FSM_DIS bit of the FSM_CONFIG register (8’h17[0]) to 1b. If fail-safe mode is enabled, the device enters fail-safe mode if any of these events occur:

  • UVCC (VCC undervoltage)
  • OVCC (VCC overvoltage)
  • TSD (thermal shutdown)
  • VCCSC (VCC short-circuit)
  • SWE timeout in standby mode

To successfully transition from fail-safe mode to normal mode, all of these faults must be cleared. Exiting this mode requires a wake event to take place, which transitions the device to restart mode. If faults are cleared, transition to normal mode can take place as described in Section 3.2.2 and Section 3.2.3. If faults are not cleared, the device will enter sleep mode after the SWE timer expires.

Each time the device enters fail-safe mode, the fail-safe mode counter is incremented. This counter (8’h18[3:0]) should be regularly set to 0 by a SPI command. Otherwise, if the counter reaches the limit (set in 8’h18[7:4]), then the action prescribed in FSM_CNTR_ACT (8’h17[7:4]) will take place.

Additionally, FS_STAT (8’h17[3:1]) provides the reason the device entered fail-safe mode, and SWE_TIMER_SET (8’h1C[6:3]) sets the length of time the SWE timer can support, ranging from 30 seconds to 10 minutes (defaulted to 5 minutes).