SLLA633 May   2024 TMDS1204

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Waking Up an HDMI Sink Device
    1. 1.1 Reasons for Wake Up Failure
  5. 2Communicating Without CEC
  6. 3HDMI1.4/2.0/2.1 Detection Methodology
  7. 4Summary
  8. 5References

2 Communicating Without CEC

The TMDS Clock Detection Solution in HDMI® Sink Applications TS3USB3031, SN65LVDS4, SN65LVDS17, application note provides examples for making the HDMI1.4/2.0 sink device detect Transition Minimized Differential Signaling (TMDS) clock or signal from an HDMI1.4/2.0 source device so that the HDMI sink can wake up from its standby state by turning on the HDMI source with a single remote controller. The HDMI transmitter source detects receiver terminations in HDMI sink. If the HDMI receiver enables the termination resistors, then the transmitter can determine the 3.3-V terminated level and that the receiver is connected and functioning.

TMDS/FRL Differential Pair Conceptional Schematic Figure 2-1 TMDS/FRL Differential Pair Conceptional Schematic

HDMI2.1 introduces a new electrical mode of operation called Fixed Rate Link (FRL). With FRL, the existing TMDS data lane 0 to 2 are re-defined as FRL data lane 0 to 2. The TMDS clock lane are re-purposed as FRL data lane 3. HDMI2.1 supports the following FRL rate and lane control.

  • 3Gbps on 3 lanes
  • 6Gbps on 3 lanes
  • 6Gbps on 4 lanes
  • 8Gbps on 4 lanes
  • 10Gbps on 4 lanes
  • 12Gbps on 4 lanes

Note, when in the FRL 3 lanes operating mode, the FRL data lane 3 is not being used.

With the TMDS clock lane being re-purposed as FRL data lane 3, the clock detection methodology being presented in TMDS Clock Detection Solution in HDMI® Sink Applications TS3USB3031, SN65LVDS4, SN65LVDS17 application note is no longer applicable and a new detection methodology is needed for HDMI2.1.