SLLSEU4E May   2016  – May 2019 TUSB1002

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, Power Supply
    6. 6.6  Electrical Characteristics
    7. 6.7  Power-Up Requirements
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Control Inputs
      2. 7.3.2 Linear Equalization
      3. 7.3.3 Adjustable VOD Linear Range and DC Gain
      4. 7.3.4 Receiver Detect Control
      5. 7.3.5 USB3.1 Dual Channel Operation (MODE = “F”)
      6. 7.3.6 USB3.1 Single Channel Operation (MODE = “1”)
      7. 7.3.7 PCIe/SATA/SATA Express Redriver Operation (MODE = “R”; CFG1 = "0"; CFG2 = "0" )
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Disconnect Mode
    5. 7.5 U0 Mode
    6. 7.6 U1 Mode
    7. 7.7 U2/U3 Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical USB3.1 Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical SATA, PCIe and SATA Express Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Detailed Design Procedure

The TUSB1002 differential receivers and transmitters have internal BIAS and termination. For this reason, the TUSB1002 must be connected to the USB3.1 host and receptacle through external A/C coupling capacitors. In this example as depicted in Table 4, 100 nF capacitors are placed on TX2P and TX2N, RX1P and RX1N, and TX1P and TX1N. 330 nF A/C coupling capacitors along with 220k resistors are placed on the RX2P and RX2N. Inclusion of these 330nF capacitors and 220k resistors is optional but highly recommended. If not implemented, then RX2P/N should be DC-coupled to the USB receptacle.

TUSB1002 Host_Impl_Schem.gifFigure 18. Host Implementation Schematic

The USB3.1 Dual channel operation is used in this example. Mode pin should be left floating (unconnected) when using this mode.

In this example, the USB3.1 Host does not support a GPIO for indicating system Sx state or low power states and therefore the SLP_S0# pin can be left floating.

The TUSB1002 compensates for channel loss in both the upstream (D to C) and downstream direction (A to B). This is done by configuring the CH1_EQ[2:1] and CH2_EQ[2:1] pins to the equalization setting that matches as close possible to the channel insertion loss. In this particular example, CH1_EQ[2:1] is for path A to B which is the channel between USB3.1 host and the TUSB1002, and CH2_EQ[2:1] is for path C to D which is the channel between TUSB1002 and the USB3.1 receptacle.

The TUSB1002 supports 5 levels of DC gain that are selected by the CFG[2:1] pins. Typically, the DC gain should be set to 0 dB but may need to be adjusted to correct any one of the following conditions:

  1. Input VID too high resulting in VOD being greater than USB 3.1 defined swing. For this case, a negative DC gain should be used.
  2. Input VID too low resulting in VOD being less than USB 3.1 defined swing. For this case, a positive DC gain should be used.
  3. Low frequency discontinuities in the channel resulting in DC component of the signal clipping the vertical eye mask. For this case, a positive DC gain should be used.

It is assumed in this example the incoming VID is at the nominal defined USB3.1 range and the channel is linear across frequency. The CFG1 and CFG2 pins can both be left floating if these assumptions are true.

In this particular example, the channel A-B has a trace length of 8 inches with a 4 mil trace width. This particular channel has about 0.83 dB per inch of insertion loss at 5 GHz. This equates to approximately 6.7 dB of loss for the entire 8 inches of trace. An additional 1.5 dB of loss is added due to package of the USB3.1 Host, TUSB1002, and the A/C coupling capacitor. This brings the entire channel loss at 5 GHz to 6.7 dB + 1.5 dB = 8.2 dB. A typical USB 3.1 host/device will have around 3 dB of transmitter de-emphasis. Transmitter de-emphasis pre-compensates for the loss of the output channel. With 3 dB of de-emphasis, the total equalization required by the TUSB1002 is in the 5.2 dB (8.2 dB - 3 dB) range. The channel A-B for this example is connected to TUSB1002's RX1P/N input and therefore CH1_EQ[2:1] pins are used for adjusting TUSB1002 RX1P/N equalization settings. The CH1_EQ[2:1] pins should be set such that TUSB1002 equalization is between 5dB and 8dB.

The channel C-D has a trace length of 4 inches with a 4mil trace width. Assuming 0.83 dB per inch of insertion loss, the 4 inch trace will equate to about 3.32 dB of loss at 5 GHz. An additional 2dB of loss needs to be added due to package, A/C coupling capacitor, and the USB 3.1 receptacle. The total loss is around 5.32 dB. Because channel C-D includes a USB 3.1 receptacle, the actual total loss could be much greater than 5.32dB due to the fact that devices plugged into the receptacle will also have loss. The device plugged into receptacle will have either a short or long channel. USB3.1 standard defines total loss limit of 23dB that is distributed as 8.5 dB for Host, 8.5dB for device, and 6.0dB for cable. With variable channel of devices plugged into the USB3.1 receptacle, configuring TUSB1002's RX2P/N equalization settings is not as straight forward as Channel A-B.

Engineer can not set TUSB1002 CH2_EQ[2:1] pins to the largest equalization setting to accommodate the largest allowed USB3.1 device/cable loss of 14.5 dB. Doing so will result in TUSB1002 operating outside its linear range when a device with short channel is plugged into the receptacle. For this reason, it is recommended to configure TUSB1002 CH2_EQ[2:1] pins to equalize a shorter device channel. This will result in requiring USB3.1 host to compensate for remaining channel loss for the worse case USB3.1 channel of 14.5 dB. The definition of a short device channel is not specified in USB 3.1 specification. Therefore, an engineer must make their own loss estimate of what constitutes a short device channel. For particular example, we will assume the short channel is around 3 to 5 dB. The device's channel loss will need to be added to estimated Channel C-D loss minus the typical 3db of de-emphasis. This means CH2_EQ[2:1] pins should be configured to handle a loss of 5 to 7 db.