SLLSF48C March   2018  – September 2019 TUSB1064

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematics
      2.      TUSB1064 Use-Case Example
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 ELECTRICAL CHARACTERISTICS
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 USB 3.1
      2. 8.3.2 DisplayPort
      3. 8.3.3 4-level Inputs
      4. 8.3.4 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 DisplayPort Mode
      4. 8.4.4 Linear EQ Configuration
      5. 8.4.5 USB3.1 Modes
      6. 8.4.6 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 11. General Registers
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
        1. Table 12. DisplayPort Control/Status Registers (0x10)
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
        1. Table 13. DisplayPort Control/Status Registers (0x11)
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
        1. Table 14. DisplayPort Control/Status Registers (0x12)
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
        1. Table 15. DisplayPort Control/Status Registers (0x13)
      6. 8.6.6 USB3.1 Control/Status Registers (address = 0x20) [reset = 00000000]
        1. Table 16. USB3.1 Control/Status Registers (0x20)
      7. 8.6.7 USB3.1 Control/Status Registers (address = 0x21) [reset = 00000000]
        1. Table 17. USB3.1 Control/Status Registers (0x21)
      8. 8.6.8 USB3.1 Control/Status Registers (address = 0x22) [reset = 00000000]
        1. Table 18. USB3.1 Control/Status Registers (0x22)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Support for DisplayPort UFP_D Pin Assignment E
      4. 9.2.4 PCB Insertion Loss Curves
    3. 9.3 System Examples
      1. 9.3.1 USB 3.1 Only
      2. 9.3.2 USB 3.1 and 2 Lanes of DisplayPort
      3. 9.3.3 DisplayPort Only
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Linear EQ Configuration

Each of the TUSB1064 receiver lanes has individual controls for receiver equalization. The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. details the gain value for each available combination when TUSB1064 is in GPIO mode. These same options are also available in I2C mode by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, DP3EQ_SEL, EQ1_SEL, EQ2_SEL, and SSEQ_SEL. Each of the 4-bit EQ configuration registers is mapped to the configuration pins as follows: x_SEL = {x1[1:0],x0[1:0]} where xn[1:0] are the EQ configuration pins with pin levels mapped to 2-bit values as: 0 = 00, R = 01, F = 10, 1 = 11.

Table 7. TUSB1064 Receiver Equalization GPIO Control

Equalization Setting # USB3.1 UPSTREAM FACING PORTS USB 3.1 DOWNSTREAM FACING PORT ALL DISPLAYPORT LANES
EQ1 PIN LEVEL EQ0 PIN LEVEL EQ GAIN at 5 GHz (dB) SSEQ1 PIN LEVEL SSEQ0 PIN LEVEL EQ GAIN at 5 GHz (dB) DPEQ1 PIN LEVEL DPEQ0 PIN LEVEL EQ GAIN at 4.05 GHz (dB)
0 0 0 -1.5 0 0 -3.0 0 0 -0.3
1 0 R 0.7 0 R -0.8 0 R 1.6
2 0 F 2.2 0 F -0.7 0 F 3.0
3 0 1 3.7 0 1 2.2 0 1 4.4
4 R 0 4.7 R 0 3.3 R 0 5.4
5 R R 5.8 R R 4.3 R R 6.5
6 R F 6.6 R F 5.1 R F 7.3
7 R 1 7.4 R 1 6.0 R 1 8.1
8 F 0 8.1 F 0 6.7 F 0 8.9
9 F R 8.7 F R 7.3 F R 9.5
10 F F 9.2 F F 7.8 F F 10.0
11 F 1 9.7 F 1 8.3 F 1 10.6
12 1 0 10 1 0 8.6 1 0 11.0
13 1 R 10.4 1 R 9.0 1 R 11.4
14 1 F 10.7 1 F 9.3 1 F 11.8
15 1 1 11.1 1 1 9.7 1 1 12.1