SLLU392 September   2024

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
    2. 2.2 Equalization Control
  8. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  9. 4Additional Information
    1. 4.1 Trademarks

2.2 Equalization Control

Equalization (EQ) can be controlled using I2C or pin-strapping. Each of the TUSB1021-Q1 receiver lanes has individual controls for receiver equalization (see Table 2-2). Reference the TUSB1021-Q1 data sheet for the gain values of each available combination of downstream and upstream configurations.

Table 2-2 Configuration Pin-Level Definitions
LevelSettings
0Option 1: Tie 1kΩ 5% to GND
Option 2: Tie directly to GND
RTie 20kΩ 5% to GND
FFloat (leave pin open)
1Option 1: Tie 1kΩ 5% to VCC
Option 2: Tie directly to VCC

The EQ0/1 pins affect the receiver EQ setting of the upstream-facing RX1 and RX2 ports, while the SSEQ0/1 pins affect the receiver EQ setting of the downstream-facing SSTX port.