SLOS197B August   1997  – July 2025 TLV2721

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics VS = 3V
    5. 5.5 Electrical Characteristics VS = 5V
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving Large Capacitive Loads
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.1.1 Driving Large Capacitive Loads

The TLV2721 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 5-27 and Figure 5-28 illustrate an ability to drive loads greater than 100pF while maintaining good gain and phase margins (Rnull = 0Ω).

A small series resistor (Rnull) at the output of the device (Figure 7-1) improves the gain and phase margins when driving large capacitive loads. Figure 5-27 and Figure 5-28 show the effects of adding series resistances of 100Ω, 200Ω, 500Ω, and 1kΩ. The addition of this series resistor has two effects: the first effect is that the resistor adds a zero to the transfer function and the second effect is that the resistor reduces the frequency of the pole associated with the output load in the transfer function.

The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To calculate the approximate improvement in phase margin, use the following equation:

Equation 1. ∆ ϕ m 1 = tan - 1 ⁡ ( 2 π × U G B W × R n u l l × C L )

Where:

∆φm1 = Improvement in phase margin

UGBW = Unity-gain bandwidth frequency

Rnull = Output series resistance

CL = Load capacitance

The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases. To use Equation 1, approximate UGBW for the given capacitive load in Figure 7-1.

TLV2721 Series Resistance Circuit Figure 7-1 Series Resistance Circuit

The TLV2721 is designed to provide better sinking and sourcing output currents than earlier CMOS rail-to-rail output devices. This device is specified to sink 500µA and source 1mA at VDD = 5V at a maximum quiescent IDD of 200µA. This provides a greater than 80% power efficiency.

When driving heavy dc loads, such as 2kΩ, the positive edge under slewing conditions can experience some distortion; see also Figure 5-22. This condition is affected by three factors:

  • Where the load is referenced. When the load is referenced to either rail, this condition does not occur. The distortion occurs only when the output signal swings through the point where the load is referenced. Figure 5-23 illustrates two 2kΩ load conditions. The first load condition shows the distortion seen for a 2kΩ load tied to 2.5V. The third load condition in Figure 5-23 shows no distortion for a 2kΩ load tied to 0V.
  • Load resistance. As the load resistance increases, the distortion seen on the output decreases. Figure 5-23 illustrates the difference seen on the output for a 2kΩ load and a 100kΩ load with both tied to 2.5V.
  • Input signal edge rate. Faster input edge rates for a step input result in more distortion than with slower input edge rates.