SLOS224L
June 1999 – July 2024
THS4031
,
THS4032
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information - THS4031
5.5
Thermal Information - THS4032
5.6
Electrical Characteristics - RL = 150Ω
5.7
Electrical Characteristics - RL = 1kΩ
5.8
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagrams
6.3
Feature Description
6.3.1
Offset Nulling
6.4
Device Functional Modes
7
Application and Implementation
7.1
Application Information
7.1.1
Driving a Capacitive Load
7.1.2
Low-Pass Filter Configurations
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Multiplexer Selection
7.2.2.2
Signal Source
7.2.2.3
Driving Amplifier
7.2.2.3.1
Driving Amplifier Bandwidth Restriction
7.2.3
Application Curves
7.3
Power Supply Recommendations
7.4
Layout
7.4.1
Layout Guidelines
7.4.1.1
General PowerPAD™ Integrated Circuit Package Design Considerations
7.4.2
Layout Example
8
Device and Documentation Support
8.1
Documentation Support
8.1.1
Related Documentation
8.2
Receiving Notification of Documentation Updates
8.3
Support Resources
8.4
Trademarks
8.5
Electrostatic Discharge Caution
8.6
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
5.2
ESD Ratings
VALUE
UNIT
V
(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(1)
±1000
V
Charged device model (CDM), per JEDEC specification JS-002
(2)
±1000
(1)
JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.