SLPU010 September   2022 JFE2140

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
    1. 1.1 JFE2140 Overview
    2. 1.2 JFE2140EVM Overview
      1. 1.2.1 Kit Contents
    3. 1.3 Related Documentation
    4. 1.4 Evaluation Module Limitations
    5. 1.5 Electrostatic Discharge Caution
  4. 2Getting Started
    1. 2.1 Power Supplies
    2. 2.2 Input
    3. 2.3 Output
    4. 2.4 Capacitors
  5. 3Application Circuit
    1. 3.1 Ultra-Low-Noise Preamplifier
  6. 4Schematic, PCB Layout, and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials

2.2 Input

The input to the JFE2140EVM interfaces high-impedance sources to the gate of the JFET. The input is ac-coupled with capacitor C3, and the dc gate bias voltage is set with resistor R13. A single SMA connector and Vin test point are available at the input to allow for an easy interface with signal generators or other equipment. Figure 3-2 shows that the midband gain of the circuit is approximately 1000 V/V or 60 dB. For example, a 1-mVpp, 1-kHz input signal produces an approximately 1-Vpp, 1-kHz signal measured on the output. The Design tools and simulation tab on the JFE2140 web folder assists with other configurations.