Q: Is there a limit to how many technical devices a user can stack?
A: The BQ77915 has no technical limitation on the number of devices in the stack. However, the larger the stack becomes, the greater the noise impact on the CTRC/D signal strength, and the greater the total delay time from the top to the bottom of the stack. This delay time is not an increase in the individual device protections, but it is a minimal increase due to logic propagation across each device in the stack. Typically this is only 1-10 ms per device added in the stack. Decide if this is a small enough margin for the application.
Q: What happens if the user configures the lower devices to support more cells than an upper devices?
A: The system must function appropriately, but TI does not recommended doing this as the CTRC/D signal strength across the stack is impacted. However, the tradeoff is lower gate voltage on the FETs. Determine which option is more effective for the specific application.
Q: What changes must be made for a device to only support three or four cells?
A: As mentioned in Section 9.3.12 in the data sheet, the CCFG pin must be configured appropriately, and the unused cells must always be selected as the uppermost cells and shorted to the immediate lower cell.