This section introduces the sampling logic of 7S battery pack and battery pack smaller than 7S in Normal Mode. For the 7S battery pack, as shown in Figure 2-1, the BQ76907 performs voltage sampling as ADSCAN LOOP.

Figure 2-1 ADSCAN LOOP for 7S Pack

Each ADSCAN LOOP contains 8 slots, of which the first 7 slots continuously collect the voltage of 7 cells, and the last slot is a shared slot.

The time T_Slot of each slot can be configured through [CVADCSPEED_1, CVADCSPEED_0]. As shown in Table 2-1. The smaller the T_Slot, the higher the sampling rate, but the lower the accuracy. On the contrary, the larger the T_Slot, the lower the sampling rate, but the higher the accuracy. Therefore, users need to compromise between the speed and accuracy of BQ76907 sampling when configuring T_Slot.

The Shared Slot is shared by (TS Pin voltage, internal temperature, VC7 Pin voltage, VREF voltage and VSS voltage). Because these voltages do not require a fast sampling rate compared to the cell voltage, each ADSCAN LOOP can only sample one of the voltages. This process takes every 5 ADSCAN LOOPs to complete the sampling of all voltages. Therefore, every 5 ADSCAN LOOPs is called a FULLSCAN LOOP, as shown in Figure 2-2.

Figure 2-2 FULLSCAN LOOP

In many application scenarios, customers do not have very high requirements for the sampling rate, but have high requirements for power consumption, and hope to maintain a relatively low power consumption level in Normal Mode. For this reason, BQ76907 opens a register: LOOP_SLOW [1, 0]. By configuring this register, users can insert several IDLE Slots after each Active Slot, and use this method to reduce the sampling rate and achieve lower power consumption. As shown in Figure 2-3.

Figure 2-3 ADSCAN LOOP with LOOP_SLOW Speed Control

Where: relationship between n and the number of IDLE slots can also be directly referred to in Table 2-2.