SLUAB40 January   2026 UCD3138A

 

  1.   1
  2.   Summary
  3. 1IBB basic control loop
  4. 2Basic configuration of UCD3138A PCM loop
  5. 3PCM failure analysis after introduction of bias voltage
  6. 4Loop correction and experimental verification
  7. 5Other debugging experience and frequently asked questions
  8. 6Summary
  9. 7References:

PCM failure analysis after introduction of bias voltage

In practical operation, UCD3138 performs two adjustments during IBB control, which are additional functions required based on theoretical control.

  1. The loop is pre-charged with the UCD3138 Blank function (a total of around 100ms) before starting the loop normally.
  2. An additional bias voltage is required for FE sampling to ensure the input voltage to FE remains positive.

For synchronous Inverse BUCK-BOOST topology power control, both voltage loop and current loop require sampling. The voltage loop generally samples the output voltage and its polarity is not reversed, so it is secure for UCD3138 Front End (FE) interface. However, in light load operation in FPWM mode, IBB, like other power supplies, will reverse the inductor current (e.g. Figure 3-1[3]).

 Inductor current reverses at light loadFigure 3-1 Inductor current reverses at light load

Therefore, when the current loop is sampled, the voltage output to FE interface may be negative, which is dangerous for UCD3138 and may damage to UCD3138.

 UCD3138A voltage input range [2]Figure 3-2 UCD3138A voltage input range [2]

Therefore, we usually need to provide a positive bias voltage to the input of FE to solve this problem, as shown in Figure 3-3, where a 0.6V positive bias voltage is applied to UCD3138 input to ensure the FE input remains positive.

 Provide 0.6V forward bias voltage to FE2Figure 3-3 Provide 0.6V forward bias voltage to FE2

Figure 3-4provides a more intuitive illustration of the differing calculation expectations for voltage loops and current loops during the pre-charge phase versus the normal operating phase in practical operation.

 Loop expectations for pre-charge phase versus normal operating modeFigure 3-4 Loop expectations for pre-charge phase versus normal operating mode

But raising this bias voltage will cause a problem. The current loop sampling value of the FE2 input will be 0.6V+Isample, so that at start-up, the sample of FE2 will have 0.6V even if there is no current. And the output voltage is 0 at start-up, so the loop will perpetually calculate an output voltage that is too low. Consequently, the pre-charge function utilizing blank time in the first stage loses control. It can be seen from the waveform that DPWM0A remains continuously on until reaching maximum duty cycle or triggering overcurrent protection.

 PCM failureFigure 3-5 PCM failure