Figure 1-1 illustrates a typical LLC resonant converter topology with a discrete capacitor structure. In the diagram, Q1 and Q2 are primary-side switches, Cr1 and Cr2 are resonant capacitors, Lr is the resonant inductor, Lm is the magnetizing inductor, and SR1 and SR2 are secondary-side synchronous rectifiers.

Figure 1-2 shows the waveforms for output short-circuit testing based on the 1kW reference design, the PMP40586. As shown in the figure, when the output is short-circuited, SR1 has an abnormal oscillating peak at its drain-to-source voltage (Vds) upon its turn-off. The maximum stress reaches 69V. This voltage exceeds the device safety margin, posing a risk of damage during repeated short circuits. Therefore, the control timing must be optimized to limit the SR stress within a safe range.