SLUS458I July   2000  – June 2024 UCC28C40 , UCC28C41 , UCC28C42 , UCC28C43 , UCC28C44 , UCC28C45 , UCC38C40 , UCC38C41 , UCC38C42 , UCC38C43 , UCC38C44 , UCC38C45

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Detailed Pin Description
        1. 7.3.1.1 COMP
        2. 7.3.1.2 FB
        3. 7.3.1.3 CS
        4. 7.3.1.4 RT/CT
        5. 7.3.1.5 GND
        6. 7.3.1.6 OUT
        7. 7.3.1.7 VDD
        8. 7.3.1.8 VREF
      2. 7.3.2  Undervoltage Lockout
      3. 7.3.3  ±1% Internal Reference Voltage
      4. 7.3.4  Current Sense and Overcurrent Limit
      5. 7.3.5  Reduced-Discharge Current Variation
      6. 7.3.6  Oscillator Synchronization
      7. 7.3.7  Soft-Start Timing
      8. 7.3.8  Enable and Disable
      9. 7.3.9  Slope Compensation
      10. 7.3.10 Voltage Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 UVLO Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Bulk Capacitor and Minimum Bulk Voltage
        2. 8.2.2.2  Transformer Turns Ratio and Maximum Duty Cycle
        3. 8.2.2.3  Transformer Inductance and Peak Currents
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Current Sensing Network
        6. 8.2.2.6  Gate Drive Resistor
        7. 8.2.2.7  VREF Capacitor
        8. 8.2.2.8  RT/CT
        9. 8.2.2.9  Start-Up Circuit
        10. 8.2.2.10 Voltage Feedback Compensation
          1. 8.2.2.10.1 Power Stage Poles and Zeroes
          2. 8.2.2.10.2 Slope Compensation
          3. 8.2.2.10.3 Open-Loop Gain
          4. 8.2.2.10.4 Compensation Loop
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Precautions
        2. 8.4.1.2 Feedback Traces
        3. 8.4.1.3 Bypass Capacitors
        4. 8.4.1.4 Compensation Components
        5. 8.4.1.5 Traces and Ground Planes
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.1 Design Requirements

Table 8-1 shows a typical set of performance requirements for an off-line flyback converter capable of providing 48W at 12V output voltage from a universal AC input. The design uses peak primary current control in a continuous current mode PWM converter.

Table 8-1 Design Parameters
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
VIN Input Voltage 85 115/230 265 VRMS
fLINE Line Frequency 47 50/60 63 Hz
VOUT Output Voltage IVOUT(min) ≤ IVOUT ≤ IVOUT(max) 11.75 12 12.25 V
VRIPPLE Output Ripple Voltage IVOUT(min) ≤ IVOUT ≤ IVOUT(max) 100 mVpp
IVOUT Output Current 0 4 A
fSW Switching Frequency 110 kHz
η Efficiency 85%