SLUS593J December   2003  – June 2022 TPS40054 , TPS40055 , TPS40057

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Setting the Switching Frequency (Programming the Clock Oscillator)
      2. 7.3.2 Programming The Ramp Generator Circuit
      3. 7.3.3 UVLO Operation
      4. 7.3.4 BP5 and BP10 Internal Voltage Regulators
      5. 7.3.5 Programming Soft Start
      6. 7.3.6 Programming Current Limit
      7. 7.3.7 Synchronizing to an External Supply
      8. 7.3.8 Loop Compensation
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Selecting the Inductor Value
      2. 8.1.2 Calculating the Output Capacitance
      3. 8.1.3 Calculating the Boost and BP10 Bypass Capacitor
      4. 8.1.4 DV-DT Induced Turn-On
      5. 8.1.5 High-Side MOSFET Power Dissipation
      6. 8.1.6 Synchronous Rectifier MOSFET Power Dissipation
      7. 8.1.7 TPS4005x Power Dissipation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Calculate Maximum and Minimum Duty Cycles
        2. 8.2.2.2  Select Switching Frequency
        3. 8.2.2.3  Select ΔI
        4. 8.2.2.4  Calculate the High-Side MOSFET Power Losses
        5. 8.2.2.5  Calculate Synchronous Rectifier Losses
        6. 8.2.2.6  Calculate the Inductor Value
        7. 8.2.2.7  Set the Switching Frequency
        8. 8.2.2.8  Program the Ramp Generator Circuit
        9. 8.2.2.9  Calculate the Output Capacitance (CO)
        10. 8.2.2.10 Calculate the Soft-Start Capacitor (CSS/SD)
        11. 8.2.2.11 Calculate the Current Limit Resistor (RILIM)
        12. 8.2.2.12 Calculate Loop Compensation Values
        13. 8.2.2.13 Calculate the Boost and BP10V Bypass Capacitance
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 MOSFET Packaging
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Loop Compensation

Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS4005x uses voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be included. The generic modulator gain is described in Figure 7-5. Duty cycle, D, varies from 0 to 1 as the control voltage, VC, varies from the minimum ramp voltage to the maximum ramp voltage, VS. Also, for a synchronous buck converter, D = VO / VIN. To get the control voltage to output voltage modulator gain in terms of the input voltage and ramp voltage:

Equation 11. GUID-8981F393-0771-432B-8D67-88618A9D9F5F-low.gif

With the voltage feedforward function, the ramp slope is proportional to the input voltage. Therefore, the moderator DC gain is independent to the change of input voltage.

For the TPS4005x, with VIN(min) being the minimum input voltage required to cause the ramp excursion to reach the maximum ramp amplitude of VRAMP, the modulator DC gain is shown in Equation 12.

Equation 12. GUID-C17315A6-F87D-4149-8CC1-8756CF8B7318-low.gif

For a buck converter using voltage mode control, there is a double pole due to the output L-CO. The double pole is located at the frequency calculated in Equation 13.

Equation 13. GUID-F38E0FBB-AD07-4BAF-8019-67B7B2EE057E-low.gif

There is also a zero created by the output capacitance, CO, and its associated ESR. The ESR zero is located at the frequency calculated in Equation 14.

Equation 14. GUID-18682173-8D38-43DD-A8BD-C8B9AC11AB06-low.gif

Calculate the value of RBIAS to set the output voltage, VO.

Equation 15. GUID-034269E8-1B35-40DD-BB0E-C0D6044EEAF6-low.gif

The maximum crossover frequency (0 dB loop gain) is set by Equation 16.

Equation 16. GUID-BE758EDB-4B96-4CDE-A671-17523F70F8F4-low.gif

Typically, fC is selected to be close to the midpoint between the L-CO double pole and the ESR zero. At this frequency, the control to output gain has a –2 slope (–40 dB/decade), while the Type III topology has a +1 slope (20 dB/decade), resulting in an overall closed loop –1 slope (–20 dB/decade). Figure 7-6 shows the modulator gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated.

GUID-67C0666B-D600-448F-9D6D-AAA8FCE0DB59-low.gif
 
 
Figure 7-5 PWM Modulator Relationships
GUID-07F9188D-175E-437C-B2F2-1824A056722A-low.gif
Figure 7-6 Modulator Gain vs Switching Frequency

A Type III topology, shown in Figure 7-7, has two zero-pole pairs in addition to a pole at the origin. The gain and phase boost of a Type III topology is shown in Figure 7-8. The two zeros are used to compensate the L-CO double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide controlled gain roll-off. In many cases, the second pole can be eliminated and the gain roll-off of the amplifier is used to roll-off the overall gain at higher frequencies.

GUID-51EED60D-E7C2-49F4-8A21-1E50982CED3C-low.gif
Figure 7-7 Type III Compensation Configuration
GUID-1EA4EC1F-C8F2-4F25-BFDA-F86C5AFA52CD-low.gif
 
 
 
 
 
 
 
Figure 7-8 Type III Compensation Gain and Phase

The poles and zeros for a Type III network are described in Equation 17 through Equation 20.

Equation 17. GUID-9508BFF6-C316-40B8-91AB-8D21E5E76C8B-low.gif
Equation 18. GUID-9949AA0E-5DE5-4252-BCBB-81908D459F7B-low.gif
Equation 19. GUID-13360AE7-A65D-4926-B651-29D833736CF6-low.gif
Equation 20. GUID-8BE494E5-7EC6-42BF-B56A-2CFDAE6A509C-low.gif

The value of R1 is somewhat arbitrary, but influences other component values. A value between 50 kΩ and 100 kΩ usually yields reasonable values.

The unity gain frequency is described in Equation 21.

Equation 21. GUID-46218670-A972-4831-BC5D-07D9292A1DB2-low.gif

where

  • G is the reciprocal of the modulator gain at fC.

The modulator gain as a function of frequency at fC is described in Equation 22.

Equation 22. GUID-F1C1AD8F-3354-4244-8CE1-8E3E783BF31A-low.gif

Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too small. The error amplifier has a finite output source and sink current, which must be considered when sizing R2. A value that is too small does not allow the output to swing over its full range.

Equation 23. GUID-FC3AE913-1D6B-4C29-B58A-505386BB6E6E-low.gif