SLUS999A November   2009  – November 2015 BQ24765

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SMB Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adapter Detect and Power Up
      2. 8.3.2  Enable and Disable Charging
      3. 8.3.3  Automatic Internal Soft-Start Charger Current
      4. 8.3.4  Switching Frequency
      5. 8.3.5  Converter Operation
      6. 8.3.6  Refresh BTST Capacitor
      7. 8.3.7  UCP (Charge Undercurrent): Using Sense Resistor
      8. 8.3.8  Cycle-By-Cycle Charge Overcurrent Protection, Using High-Side Sense-FET
      9. 8.3.9  Average Charge Overcurrent Protection, Using Sense Resistor
      10. 8.3.10 Battery Overvoltage Protection, Using Remote Sensing VFB
      11. 8.3.11 Battery Short Protection
      12. 8.3.12 Battery Trickle Charging
      13. 8.3.13 High Accuracy VICM Using Current Sense Amplifier (CSA)
      14. 8.3.14 VDDSMB Input Supply
      15. 8.3.15 Input Undervoltage Lockout (UVLO)
      16. 8.3.16 VDDP Gate Drive Regulator
      17. 8.3.17 Input Current Comparator Trip Detection
      18. 8.3.18 Open-Drain Status Outputs (ACOK, ICOUT Pins)
      19. 8.3.19 Thermal Shutdown Protection
      20. 8.3.20 Charger Timeout
      21. 8.3.21 Charge Termination For Li-Ion or Li-Polymer
      22. 8.3.22 Remote Sense
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conduction Mode and Discontinuous Conduction Mode
    5. 8.5 Programming
      1. 8.5.1 Battery-Charger Commands
        1. 8.5.1.1 SMBus Interface
      2. 8.5.2 Battery Voltage Regulation
      3. 8.5.3 Battery Current Regulation
      4. 8.5.4 Input Adapter Current Regulation
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Voltage DCINP, DCINA, CSOP, CSON, CSSP, CSSN, VFB, ACOK –0.3 30 V
PHASE –1 30
EAI, EAO, FBO, VDDP, ACIN, VICM, ICOUT, ICREF, CE –0.3 7
VDDSMB, SDA, SCL –0.3 6
VREF –0.3 3.6
BOOT (with respect to AGND and PGND) –0.3 36
Maximum difference voltage: CSOP–CSON, CSSP–CSSN –0.5 0.5 V
Operating junction temperature, TJ -40 155 °C
Storage temperature, Tstg –55 155 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to AGND and PGND if not specified. Currents are positive into, and negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Voltage PHASE –1 24 V
DCINP, DCINA, CSOP, CSON, CSSP, CSSN, VFB, ACOK 0 24
VDDP 0 6.5
VREF 3.3
VDDSMB, SDA, SCL 0 5.5
EAI, EAO, FBO, ACIN, VICM, ICOUT, ICREF, CE 0 5.5
BOOT (with respect to GND and PGND) 0 30
Maximum difference voltage: CSOP–CSON, CSSP–CSSN –0.3 0.3 V
Junction temperature –40 125 °C
Storage temperature –55 150 °C

7.4 Thermal Information

THERMAL METRIC(1) bq24765 UNIT
RUV (VQFN)
34 PINS
RθJA Junction-to-ambient thermal resistance 33.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 23 °C/W
RθJB Junction-to-board thermal resistance 6.3 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 6.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

7.0 V ≤ V(DCINA) ≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CONDITIONS
VDCIN_OP DCINA/DCINP input voltage operating range 7 24 V
CHARGE VOLTAGE REGULATION
VVFB_OP VFB input voltage range 0 DCINA V
VVFB_REG_ACC VFB charge voltage regulation accuracy ChargeVoltage() = 0x41A0 16.716 16.8 16.884 V
–0.5% 0.5%
ChargeVoltage() = 0x3130 12.529 12.592 12.655 V
–0.5% 0.5%
ChargeVoltage() = 0x20D0 8.350 8.4 8.450 V
–0.6% 0.6%
VVFB_REG_RNG Charge voltage regulation range 1.024 19.2 V
CHARGE CURRENT REGULATION
VIREG_CHG_RNG Charge current regulation differential voltage range VIREG_CHG = VCSOP – VCSON, Maximum charge current is 8.064 A with 10-mΩ sense resistor. 0 8064 mV
ICHRG_REG_ACC Charge current regulation accuracy ChargeCurrent() = 0x0F80 3968 mA
–3% 3%
ChargeCurrent() = 0x0800 2048 mA
–5% 5%
ChargeCurrent() = 0x0200 512 mA
–25% 25%
ChargeCurrent() = 0x0080 128 mA
–33% 33%
INPUT CURRENT REGULATION
VIREG_DPM_RNG Adapter current regulation differential voltage range VIREG_DPM = VCSSP – VCSSN 0 110.08 mV
IINPUT_REG_ACC Input current regulation accuracy InputCurrent() ≥ 0x0800 4096 mA
–3% 3%
InputCurrent() = 0x0400 2048 mA
–5% 5%
InputCurrent() = 0x0100 512 mA
–25% 25%
InputCurrent() = 0x0080 256 mA
–33% 33%
THERMAL REGULATION
TJ_REG_ACC Junction temperature regulation accuracy CE=High; Charging 110 120 130 °C
VREF REGULATOR
VVREF_REG VREF regulator voltage VDCIN > VDCIN_UVLO; VACIN > 0.6 V 3.267 3.3 3.333 V
IVREF_LIM VREF current limit VVREF = 0 V, VDCIN_UVLO; VACIN > 0.6 V 35 75 mA
VDDP REGULATOR
VVDDP_REG VDDP regulator voltage VDCIN > VDCIN_UVLO; VACIN > 2.4 V, CE=High 5.7 6.0 6.3 V
IVDDP_LIM VDDP current limit VVDDP = 0 V, VDCIN > VDCIN_UVLO;
VACIN > 2.4 V, CE=High		 90 135 mA
VVDDP = 5 V, VDCIN > VDCIN_UVLO;
VACIN > 2.4 V, CE=High		 80
ADAPTER CURRENT SENSE AMPLIFIER
VCSSP/N_OP Input common mode Voltage on CSSP/CSSN 0 24 V
VVICM VICM output voltage 0 2 V
IVICM VICM Output Current 0 1 mA
AVICM Current sense amplifier voltage gain AVICM = VVICM/ VIREG_DPM 20 V/V
Adapter current sense accuracy VIREG_DPM = V(CSSP–CSSN) ≥ 40 mV –2% 2%
VIREG_DPM = V(CSSP–CSSN) = 20 mV –3% 3%
VIREG_DPM = V(CSSP–CSSN) = 5 mV –25% 25%
VIREG_DPM = V(CSSP–CSSN) = 1.5 mV –33% 33%
IVICM_LIM Output current limit VVICM = 0 V 1 mA
CVICM_MAX Maximum output load capacitance For stability with 0-mA to 1-mA load 100 pF
ACIN COMPARATOR (Adapter Detect)
VDCIN_VFB_OP Differential voltage from DCINA to VFB –20 24 V
VACIN_CHG ACIN rising threshold Min voltage to enable charging, VACIN rising 2.376 2.40 2.424 V
VACIN_CHG_HYS ACIN falling hysteresis VACIN falling 40 mV
ACIN rising deglitch (1) VACIN rising 100 μs
VACIN_BIAS Adapter present rising threshold Min voltage to enable all bias, VACIN rising 0.56 0.62 0.68 V
VACIN_BIAS_HYS Adapter present falling hysteresis VACIN falling 20 mV
V(DCIN–VFB) COMPARATOR (Reverse Discharging Protection)
VDCIN-VFB_FALL DCIN to VFB falling threshold VDCIN – VVFB falling 140 185 240 mV
VDCIN-VFB__HYS DCIN to VFB hysteresis 50 mV
DCIN to VFB rising deglitch VDCIN – VVFB > VDCIN-VFB_RISE 1 ms
VFB OVERVOLTAGE COMPARATOR
VOV_RISE Over-voltage rising threshold As percentage of VVFB_REG 104%
VOV_FALL Over-voltage falling threshold As percentage of VVFB_REG 102%
VFB BATSHORT COMPARATOR (Undervoltage)
VVFB_SHORT_RISE VFB short rising threshold 2.6 2.7 2.85 V
VVFB_SHORT_HYS VFB short falling hysteresis 250 mV
VVFB_SHORT_ICHG VFB short precharge current 60 220 mA
VFB BATLOWV COMPARATOR
VVFB_LOWV_RISE VFB LOWV rising threshold 3.9 4 4.1 V
VVFB_LOWV_HYS VFB LOWV falling hysteresis 400 mV
VFB LOWV one-shot reset time Time to time charger 2 ms
VVFB_LOWV_ICHG VFB LOWV max DAC output VFB falling, on 10-mΩ resistor 3 A
CHARGE OVER-CURRENT COMPARATOR – Average current using sense resistor
Charge overcurrent falling threshold V(CSOP-CSON) > 33 mV, as percentage of IREG_CHG 145%
Minimum current limit V(CSOP-CSON) < 33 mV 50 mV
Internal filter pole frequency 160 kHz
CHARGE OVER-CURRENT COMPARATOR – Cycle-by-Cycle Maximum current using High-Side SenseFet
VOCP_CycleByCycle Charge over-current rising threshold, latches off high-side MOSFET until next cycle. High-side drain current rising-edge. 8 10 12 A
DCIN INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)
VDCIN_UVLO DCINA undervoltage rising threshold Measure on DCINA pin 3.5 4 4.5 V
VDCIN_UVLO_HYS DCINA undervoltage hysteresis, falling 260 mV
INPUT CURRENT COMPARATOR
VICCOMP_OFFSET AC low power mode comparator offset voltage On ICREF –8 8 mV
THERMAL SHUTDOWN COMPARATOR
TSHUT Thermal shutdown threshold with rising temperature Temperature rising 155 °C
TSHUT_HYS Thermal shutdown hysteresis, falling Temperature falling 20
PWM HIGH SIDE POWER MOSFET
RDSON_HI High side power MOSFET drain to source on resistance VBOOT – VPHASE = 5.5 V, Drain current = 4 A, TJ = 25°C 27 32 mΩ
VBOOT – VPHASE = 5.5 V, Drain current = 4 A, TJ = 0 to 125°C 27 46
VBOOT_REFRESH Bootstrap refresh comparator threshold voltage VBOOT – VPHASE when low side refresh pulse is requested 4 V
IBOOT_LEAK BOOT leakage current High Side is on; Charge enabled 200 μA
PWM LOW SIDE POWER MOSFET
RDS_LO_ON Low side power MOSFET drain to source on resistance VVDDP = 6 V, Drain Current = 4 A, TJ = 25°C 38 45 mΩ
VVDDP = 6 V, Drain Current = 4 A, TJ = 0 to 125°C 38 66
PWM DRIVERS TIMING
Minimum driver dead time Dead time when switching between High-Side MOSFET and Low-Side MOSFET. Adaptive protective dead-time could be more. 25 ns
PWM OSCILLATOR
FSW PWM switching frequency 540 700 840 kHz
VRAMP_OFFSET PWM ramp offset 200 mV
VRAMP_HEIGHT PWM ramp height As percentage of DCINA 6.67 %DCINA
QUIESCENT CURRENT
IOFF_STATE Total off-state battery current from CSOP, CSON, VFB, DCINA, DCINP, BOOT, PHASE, etc., Adapter removed VVFB = 16.8 V, VACIN < 0.6 V,
VDCINA > 5 V, ≤ TJ = 0°C to 85°C		 7 10 μA
IBAT_ON Battery on-state quiescent current VVFB = 16.8 V, 0.6 V < VACIN < 2.4 V,
VDCINA > 5 V 		1 mA
IBAT_LOAD_CD Internal battery load current,during charge disabled, adapter connected Charge is disabled: VVFB = 16.8 V,
VACIN > 2.4 V, VDCINA > 5 V		 0.5 1 mA
IBAT_LOAD_CE Internal battery load current during charge enabled, charging. CSOP, CSON, VFB, BOOT, PHASE CE = high, VVFB = 16.8 V,
VACIN > 2.4 V, VDCINA > 5 V		 6 10 12 mA
IAC Adapter quiescent current, charge disabled CE = low, VDCINA = 20 V 0.5 1 mA
IAC_SWITCH Adapter switching quiescent current Charge enabled, VDCINA = 20 V, converter switching 25 mA
INTERNAL SOFT START (8 Steps to Regulation Current ICHG)
Soft start steps 8 step
Soft start step time 1.6 ms
CHARGER SECTION POWER-UP SEQUENCING
Charge-Enable Delay after Power-up Delay from when adapter is detected and CE is high to when the charger is allowed to turn on 2 ms
CHARGE UNDERCURRENT COMPARATOR (Cycle-by-Cycle Synchronous to Non-Synchronous)
VUCP Cycle-by-cycle Synchronous to Non-Synchronous Transition Threshold Cycle-by-cycle, (CSOP-CSON) voltage, falling, LGATE turns-off and latches off until next cycle 5 10 15 mV
LOGIC INPUT PIN CHARACTERISTICS (CE, SDA, SCL)
VIN_LO Input low threshold voltage 0.8 V
VIN_HI Input high threshold voltage Pull-up CE with ≥ 2 kΩ resistor, or connect directly to VREF. 2.1 V
VBIAS Input bias current V = 0 to 7 V 1 μA
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (ACOK, ICOUT)
VOUT_LO Output low saturation voltage Sink Current = 5 mA 0.5 V
VDDSMB INPUT SUPPLY FOR SMBUS
VVDDSMB_RANGE VDDSMB input voltage range 2.7 5.5 V
VVDDSMB_UVLO_ Threshold_Rising VDDSMB undervoltage lockout threshold voltage, rising VVDDSMB Rising 2.4 2.5 2.6 V
VVDDSMB_UVLO_ Hyst_Rising VDDSMB undervoltage lockout hysteresis voltage, falling VVDDSMB Falling 100 150 200 mV
IVDDSMB_Iq VDDSMB quiescent current VVDDSMB = SCL = SDA = 3.3 V 20 30 μA
(1) Verified by design.

7.6 SMB Timing Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR SCLK/SDATA rise time 1 µs
tF SCLK/SDATA fall time 300 ns
tW(H) SCLK pulse width high 4 50 µs
tW(L) SCLK Pulse Width Low 4.7 µs
tSU(STA) Setup time for START condition 4.7 µs
tH(STA) START condition hold time after which first clock pulse is generated 4 µs
tSU(DAT) Data setup time 250 ns
tH(DAT) Data hold time 300 ns
tSU(STOP) Setup time for STOP condition 4 µs
t(BUF) Bus free time between START and STOP condition 4.7 µs
FS(CL) Clock Frequency 10 100 kHz
HOST COMMUNICATION FAILURE
ttimeout SMBus bus release timeout 22 25 35 ms
tBOOT Deglitch for watchdog reset signal 10 ms
tWDI Watchdog timeout period 140 170 200 s
OUTPUT BUFFER CHARACTERISTICS
V(SDAL) Output LO voltage at SDA, I(SDA) = 3 mA 0.4 V
bq24765 smbus_tim_lus999.gif Figure 1. SMBus Communication Timing Waveforms

7.7 Typical Characteristics

bq24765 G1_lus999.gif Figure 2. VREF Load and Line Regulation vs Load Current
bq24765 G3_lus999.gif Figure 4. VFB Voltage Regulation Accuracy vs Charge Current
bq24765 G5_lus999.gif Figure 6. Charge Current Regulation Accuracy vs V(CSOP-CSON) Voltage Set Point
bq24765 G7_lus999.gif Figure 8. Efficiency vs Battery Charge Current
bq24765 G9_lus999.gif Figure 10. VICM Input Current Sense Amplifier Accuracy vs V(CSSP-CSSN) Voltage
bq24765 G11_lus999.gif Figure 12. Input Regulation Current (DPM), and Charge Current Accuracy vs System Current
bq24765 G2_lus999.gif Figure 3. VDDP Load and Line Regulation vs Load Current
bq24765 G4_lus999.gif Figure 5. VFB Voltage Regulation Accuracy vs Set Point
bq24765 G6_lus999.gif Figure 7. Charge Current Regulation vs VFB Voltage
bq24765 G8_lus999.gif Figure 9. Input Current Regulation (DPM) Accuracy vs V(CSSP-CSSN) Voltage Set Point
bq24765 G10_lus999.gif Figure 11. Input Regulation Current (DPM) and Charge Current vs System Current