SLUSAL0C September   2011  – January 2020 BQ24725A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SMBus Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adapter Detect and ACOK Output
      2. 8.4.2  Adapter Over Voltage (ACOVP)
      3. 8.4.3  System Power Selection
      4. 8.4.4  Battery LEARN Cycle
      5. 8.4.5  Enable and Disable Charging
      6. 8.4.6  Automatic Internal Soft-Start Charger Current
      7. 8.4.7  High Accuracy Current Sense Amplifier
      8. 8.4.8  Charge Timeout
      9. 8.4.9  Converter Operation
      10. 8.4.10 Continuous Conduction Mode (CCM)
      11. 8.4.11 Discontinuous Conduction Mode (DCM)
      12. 8.4.12 Input Over Current Protection (ACOC)
      13. 8.4.13 Charge Over Current Protection (CHGOCP)
      14. 8.4.14 Battery Over Voltage Protection (BATOVP)
      15. 8.4.15 Battery Shorted to Ground (BATLOWV)
      16. 8.4.16 Thermal Shutdown Protection (TSHUT)
      17. 8.4.17 EMI Switching Frequency Adjust
      18. 8.4.18 Inductor Short, MOSFET Short Protection
    5. 8.5 Register Maps
      1. 8.5.1 Battery-Charger Commands
      2. 8.5.2 Setting Charger Options
        1. Table 3. Charge Options Register (0x12H)
      3. 8.5.3 Setting the Charge Current
        1. Table 4. Charge Current Register (0x14H), Using 10mΩ Sense Resistor
      4. 8.5.4 Setting the Charge Voltage
        1. Table 5. Charge Voltage Register (0x15H)
      5. 8.5.5 Setting Input Current
        1. Table 6. Input Current Register (0x3FH), Using 10mΩ Sense Resistor
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical System with Two NMOS Selector
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Negative Output Voltage Protection
          2. 9.2.1.2.2 Reverse Input Voltage Protection
          3. 9.2.1.2.3 Reduce Battery Quiescent Current
          4. 9.2.1.2.4 Inductor Selection
          5. 9.2.1.2.5 Input Capacitor
          6. 9.2.1.2.6 Output Capacitor
          7. 9.2.1.2.7 Power MOSFETs Selection
          8. 9.2.1.2.8 Input Filter Design
          9. 9.2.1.2.9 BQ24725A Design Guideline
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Simplified System without Power Path
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6.6 Timing Characteristics

4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
SMBus TIMING CHARACTERISTICS
tR SCLK/SDATA rise time 1 μs
tF SCLK/SDATA fall time 300 ns
tW(H) SCLK pulse width high 4 50 μs
tW(L) SCLK Pulse Width Low 4.7 μs
tSU(STA) Setup time for START condition 4.7 μs
tH(STA) START condition hold time after which first clock pulse is generated 4 μs
tSU(DAT) Data setup time 250 ns
tH(DAT) Data hold time 300 ns
tSU(STOP) Setup time for STOP condition 4 µs
t(BUF) Bus free time between START and STOP condition 4.7 μs
FS(CL) Clock Frequency 10 100 kHz
HOST COMMUNICATION FAILURE
ttimeout SMBus bus release timeout(2) 25 35 ms
tBOOT Deglitch for watchdog reset signal 10 ms
tWDI Watchdog timeout period, ChargeOption() bit [14:13] = 01(3) 35 44 53 s
Watchdog timeout period, ChargeOption() bit [14:13] = 10(3) 70 88 105 s
Watchdog timeout period, ChargeOption() bit [14:13] = 11(3) (Default) 140 175 210 s