SLUSAM3A May   2011  – December 2016 BQ76PL536A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: AC SPI Data Interface
    7. 6.7 Vertical Communications Bus
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog-to-Digital Conversion (ADC)
        1. 7.3.1.1  General Features
        2. 7.3.1.2  3-to-6 Series Cell Configuration
        3. 7.3.1.3  Cell Voltage Measurements
        4. 7.3.1.4  GPAI or VBAT Measurements
          1. 7.3.1.4.1 Converting GPAI Result to Voltage
          2. 7.3.1.4.2 Converting VBAT Result to Voltage
        5. 7.3.1.5  Temperature Measurement
          1. 7.3.1.5.1 External Temperature Sensor Support (TS1+, TS1-, TS2+, and TS2-)
          2. 7.3.1.5.2 Converting TSn Result to Voltage (Ratio)
        6. 7.3.1.6  ADC Band-Gap Voltage Reference
        7. 7.3.1.7  Conversion Control
          1. 7.3.1.7.1 Convert Start
            1. 7.3.1.7.1.1 Hardware Start
            2. 7.3.1.7.1.2 Firmware Start
          2. 7.3.1.7.2 Data Ready
          3. 7.3.1.7.3 ADC Channel Selection
          4. 7.3.1.7.4 Conversion Time Control
          5. 7.3.1.7.5 Automatic Versus Manual Control
        8. 7.3.1.8  Secondary Protection
          1. 7.3.1.8.1 Protector Functionality
            1. 7.3.1.8.1.1 Using the Protector Functions With 3-5 Cells
        9. 7.3.1.9  Cell Overvoltage Fault Detection (COV)
        10. 7.3.1.10 Cell Undervoltage Fault Detection (CUV)
        11. 7.3.1.11 Overtemperature Detection
          1. 7.3.1.11.1 Ratiometric Sensing
          2. 7.3.1.11.2 Thermistor Power
          3. 7.3.1.11.3 Thermistor Input Conditioning
        12. 7.3.1.12 Fault and Alert Behavior
          1. 7.3.1.12.1 Fault Recovery Procedure
        13. 7.3.1.13 Secondary Protector Built-In Self-Test Features
      2. 7.3.2 Cell Balancing
        1. 7.3.2.1 Cell Balance Control Safety Timer
      3. 7.3.3 Other Features and Functions
        1. 7.3.3.1 Internal Voltage Regulators
          1. 7.3.3.1.1 Internal 5-V Analog Supply
          2. 7.3.3.1.2 Internal 5-V Digital Supply
          3. 7.3.3.1.3 Low-Dropout Regulator (REG50)
          4. 7.3.3.1.4 Auxiliary Power Output (AUX)
        2. 7.3.3.2 Undervoltage Lockout and Power-On Reset
          1. 7.3.3.2.1 UVLO
          2. 7.3.3.2.2 Power-On Reset (POR)
          3. 7.3.3.2.3 Reset Command
        3. 7.3.3.3 Thermal Shutdown (TSD)
        4. 7.3.3.4 GPIO
      4. 7.3.4 Communications
        1. 7.3.4.1 SPI Communications - Device to Host
        2. 7.3.4.2 Device-to-Device Vertical Bus (VBUS) Interface
        3. 7.3.4.3 Packet Formats
          1. 7.3.4.3.1 Data Read Packet
          2. 7.3.4.3.2 Data Write Packet
          3. 7.3.4.3.3 Broadcast Writes
          4. 7.3.4.3.4 Communications Packet Structure
          5. 7.3.4.3.5 CRC Algorithm
          6. 7.3.4.3.6 Data Packet Usage Examples
        4. 7.3.4.4 Device Addressing
    4. 7.4 Device Functional Modes
      1. 7.4.1 SLEEP Functionality
        1. 7.4.1.1 SLEEP State Entry (Bit Set)
        2. 7.4.1.2 SLEEP State Exit (Bit Reset)
    5. 7.5 Programming
      1. 7.5.1 Programming the EPROM Configuration Registers
    6. 7.6 Register Maps
      1. 7.6.1 I/O Register Details
      2. 7.6.2 Register Types
        1. 7.6.2.1 Read-Only (Group 1)
        2. 7.6.2.2 Read / Write (Group 2)
        3. 7.6.2.3 Read / Write, Initialized From EPROM (Group3)
        4. 7.6.2.4 Error Checking and Correcting (ECC) EPROM
      3. 7.6.3 Register Details
        1. 7.6.3.1  DEVICE_STATUS Register (0x00)
        2. 7.6.3.2  GPAI (0x01, 0x02) Register
        3. 7.6.3.3  VCELLn Register (0x03…0x0e)
        4. 7.6.3.4  TEMPERATURE1 Register (0x0f, 0x10)
        5. 7.6.3.5  TEMPERATURE2 Register (0x11, 0x12)
        6. 7.6.3.6  ALERT_STATUS Register (0x20)
        7. 7.6.3.7  FAULT_STATUS Register (0x21)
        8. 7.6.3.8  COV_FAULT Register (0x22)
        9. 7.6.3.9  CUV_FAULT Register (0x23)
        10. 7.6.3.10 PARITY_H Register (0x24) [PRESULT_A (R/O)]
        11. 7.6.3.11 PARITY_H Register (0x25) [PRESULT_B (R/O)]
        12. 7.6.3.12 ADC_CONTROL Register (0x30)
        13. 7.6.3.13 IO_CONTROL Register (0x31)
        14. 7.6.3.14 CB_CTRL Register (0x32)
        15. 7.6.3.15 CB_TIME Register (0x33)
        16. 7.6.3.16 ADC_CONVERT Register (0x34)
        17. 7.6.3.17 SHDW_CTRL Register (0x3a)
        18. 7.6.3.18 ADDRESS_CONTROL Register (0x3b)
        19. 7.6.3.19 RESET Register (0x3c)
        20. 7.6.3.20 TEST_SELECT Register (0x3d)
        21. 7.6.3.21 E_EN Register (0x3f)
        22. 7.6.3.22 FUNCTION_CONFIG Register (0x40)
        23. 7.6.3.23 IO_CONFIG Register (0x41)
        24. 7.6.3.24 CONFIG_COV Register (0x42)
        25. 7.6.3.25 CONFIG_COVT Register (0x43)
        26. 7.6.3.26 CONFIG_UV Register (0x44)
        27. 7.6.3.27 CONFIG_CUVT Register (0x45)
        28. 7.6.3.28 CONFIG_OT Register (0x46)
        29. 7.6.3.29 CONFIG_OTT Register (0x47)
        30. 7.6.3.30 USERx Register (0x48-0x4b) (USER1-4)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Anti-Aliasing Filter
      2. 8.1.2 Host SPI Interface Pin States
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Decoupling
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

PAP Package
64-Pin HTQFP
Top View
bq76PL536A-Q1 P0071-04_LUSA08.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 15 AI Internal analog VREF (–)
ALERT_H 38 O Host-to-device interface – ALERT condition detected in this or higher (North) device
ALERT_N 57 I Current-mode input indicating a system status change from the next-higher bq76PL536A-Q1
ALERT_S 23 OD Current-mode output indicating a system status change to the next lower bq76PL536A-Q1
AUX 31 O Switched current-limited output from REG50
BAT1 63 P Power-supply voltage, connect to most-positive cell +, tie to BAT2 on PCB
BAT2 64 P Power-supply voltage, connect to most-positive cell +, tie to BAT1 on PCB
CB1 12 O Cell-balance control output 1
CB2 10 O Cell-balance control output 2
CB3 8 O Cell-balance control output 3
CB4 6 O Cell-balance control output 4
CB5 4 O Cell-balance control output 5
CB6 2 O Cell-balance control output 6
CONV_H 36 I Host-to-device interface – initiates a synchronous conversion. Pin has 250-nA internal sink to VSS.
CONV_N 59 OD Current-mode output to the next-higher bq76PL536A-Q1 to initiate a conversion
CONV_S 21 I Input from the adjacent lower bq76PL536A-Q1 to initiate a conversion
CS_H 43 I Host-to-device interface – active-low chip select from host. Internal 100-kΩ pull-up resistor
CS_N 52 OD Current-mode output used to select the next-higher bq76PL536A-Q1 for SPI communication
CS_S 29 I Current-mode input SPI chip-select (slave-select) from the next-lower bq76PL536A-Q1
DRDY_H 37 O Host-to-device interface – conversion complete, data-ready indication
DRDY_N 58 I Current-mode input indicating conversion data is ready from next-higher bq76PL536A-Q1
DRDY_S 22 OD Current-mode output indicating conversion data is ready to the next lower bq76PL536A-Q1
FAULT_H 39 O Host-to-device interface – FAULT condition detected in this or higher (North) device
FAULT_N 56 I Current-mode input indicating a system status change from the next-higher bq76PL536A-Q1
FAULT_S 24 OD Current-mode output
GPAI+ 48 AI General-purpose (differential) analog input, connect to VSS if unused.
GPAI– 47 AI General-purpose (differential) analog input, connect to VSS if unused.
GPIO 45 IOD Digital open-drain I/O. A 10-kΩ to 2-MΩ pull-up is recommended.
HSEL 44 I Host interface enable, 0 = enable, 1 = disable
LDOA 17 P Internal analog 5-V LDO bypass connection, requires 2.2-µF ceramic capacitor for stability
LDOD1 18 P Internal digital 5-V LDO bypass connection 1, requires 2.2-µF ceramic capacitor for stability. This pin is tied internally to LDOD2. This pin should be tied to LDOD2 externally.
LDOD2 46 P Internal digital 5-V LDO bypass connection 2, requires 2.2-µF ceramic capacitor for stability. This pin is tied internally to LDOD1. This pin should be tied to LDOD1 externally.
NC30 30 — No connection
NC51 51 — No connection
NC62 62 — No connection
REG50 32 P 5-V user LDO output, requires 2.2-µF ceramic capacitor for stability
SCLK_H 40 I Host-to-device interface – SPI clock from host
SCLK_N 55 OD Current-mode output SPI clock to the next-higher bq76PL536A-Q1
SCLK_S 26 I Current-mode input SPI clock from the next-lower bq76PL536A-Q1
SDI_H 42 I Host-to-device interface – data from host to device (host MOSI signal)
SDI_N 53 OD Current-mode output for SPI data to the next-higher bq76PL536A-Q1
SDI_S 28 I Current-mode input for SPI data from the next-lower bq76PL536A-Q1
SDO_H 41 O Host-to-device interface – data from device to host (host MISO signal), 3-state pin, 250-nA internal pull-up
SDO_N 54 I Current-mode input for SPI data from the next-lower bq76PL536A-Q1
SDO_S 27 OD Current-mode output for SPI data to the next-lower bq76PL536A-Q1
TEST 50 I Factory test pin. Connect to VSS in user circuitry. This pin includes an approximately 100-kΩ internal pull-down
TS1+ 20 AI Differential temperature sensor input
TS1– 19 AI Differential temperature sensor input
TS2+ 61 AI Differential temperature sensor input
TS2– 60 AI Differential temperature sensor input
VC0 13 AI Sense-voltage input terminal for negative terminal of first cell (VSS)
VC1 11 AI Sense voltage input terminal for positive terminal of the first cell
VC2 9 AI Sense voltage input terminal for the positive terminal of the second cell
VC3 7 AI Sense voltage input terminal for the positive terminal of the third cell
VC4 5 AI Sense voltage input terminal for the positive terminal of the fourth cell
VC5 3 AI Sense voltage input terminal for the positive terminal of the fifth cell
VC6 1 AI Sense voltage input terminal for the positive terminal of the sixth cell
VREF 16 P Internal analog voltage reference (+), requires 10-µF, low-ESR ceramic capacitor to AGND for stability
VSS 14, 33, 34, 35 P VSS
VSSD 25, 49 P VSS
Thermal pad — — Thermal pad on bottom of PowerPAD™ package; this must be soldered to similar-size copper area on PCB and connected to VSS, to meet stated specifications herein. Provides heat-sinking to part.
  1. Key: I = digital input, AI = analog input, O = digital output, OD = open-drain output, T = 3-state output, P = power.