SLUSFC0 September   2024 LMG3614

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 GaN Power FET Switching Capability
      2. 7.3.2 Turn-On Slew-Rate Control
      3. 7.3.3 Input Control Pin (IN)
      4. 7.3.4 AUX Supply Pin
        1. 7.3.4.1 AUX Power-On Reset
        2. 7.3.4.2 AUX Under-Voltage Lockout (UVLO)
      5. 7.3.5 Overtemperature Protection
      6. 7.3.6 Fault Reporting
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Turn-On Slew-Rate Design
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

Figure 4-1 REQ Package, 38-Pin VQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
NC1 1, 15 NC Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to D.
D 2-14 P GaN FET drain. Internally connected to NC1.
NC2 16, 20, 38 NC Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Internally connected to AGND, S and, PAD.
S 17-19, 21-29 P GaN FET source. Internally connected to AGND, PAD, and NC2.
NC3 30 NC Pin is not functional. Do not connect PCB landing pad to other metal. Internally connected to AGND through active impedance.
IN 31 I Gate-drive control input. There is a forward based ESD diode from IN to AUX so avoid driving IN higher than AUX.
AGND 32 GND Analog ground. Internally connected to S, PAD, and NC2.
NC4 33 NC Pin is not functional. Do not connect PCB landing pad to other metal. Internally connected to AGND through active impedance.
NC5 34 NC Used to anchor QFN package to PCB. Pin must be soldered to a PCB landing pad. The PCB landing pad is non-solder mask defined pads and must not be physically connected to any other metal on the PCB. Pin not connected internally.
FLT 35 O Active-low fault output. Open-drain output that asserts during overtemperature protection.
AUX 36 P Auxiliary voltage rail. Device supply voltage. Connect a local bypass capacitor between AUX and AGND.
RDRV 37 I Drive strength control resistor. Set a resistance between RDRV and AGND to program the GaN FET turn-on slew rate.
PAD — — Thermal pad. Internally connected to S, AGND, and NC2. All the S current may be conducted with PAD (PAD = S).
(1) I = input, O = output, I/O = input or output, GND = ground, P = power, NC = no connect.