SLUUCU0B April   2023  – September 2023 TPSM863252 , TPSM863253 , TPSM863257

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Performance Specification Summary
  6. 3Output Voltage Setpoint
  7. 4Test Setup and Results
    1. 4.1 Input and Output Connections
    2. 4.2 Start-Up Procedure
    3. 4.3 Efficiency
    4. 4.4 Load Regulation
    5. 4.5 Line Regulation
    6. 4.6 Load Transient Response
    7. 4.7 Start-Up
    8. 4.8 Shutdown
    9. 4.9 Output Voltage Ripple
  8. 5Board Layout
    1. 5.1 Layout
  9. 6Schematic, Bill of Materials
    1. 6.1 Schematic
    2. 6.2 Bill of Materials
  10. 7Related Documentation
  11. 8Revision History

4.1 Input and Output Connections

The TPSM863252EVM is provided with input and output connectors and test points as shown in Table 4-1. Figure 4-1 shows connectors and jumpers placement on the TPSM863252EVM board.

A power supply capable of supplying 3 A must be connected to J1 through a pair of 20-AWG wires. The load must be connected to J2 through a pair of 20-AWG wires. The maximum load current capability is 3 A. Wire lengths must be minimized to reduce losses in the wires. The TP1 provides a place to monitor the VIN input voltages with TP2 providing a convenient ground reference. TP3 is used to monitor the output voltage with TP4 as the ground reference.

GUID-20230320-SS0I-VJRX-1MWW-LKSKJBWXBBBW-low.svgFigure 4-1 TPSM863252EVM Connectors and Jumpers Placement
Table 4-1 Connection and Test Points
Reference DesignatorFunction
J1VIN (see Table 1-1 for VIN range)
J2VOUT, 1.05 V at 3-A maximum
J3Source selection for PGOOD, Short pin 1 and pin 2, PG is pull high to Vout
TP1VIN positive power point
TP2, TP4GND power point
TP3VOUT positive power point
TP5EN test point
TP6Switch node test point
TP7PGOOD test point
TP8Test point for loop response measurements
TP9, TP10GND monitor point