SLUUDF9A January   2026  – July 2026 LMK3H2108

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Configuration Overview
    1. 1.1 LMK3H2108A19 Configuration Information
  5. 2Revision History

1.1 LMK3H2108A19 Configuration Information

Table 1-1 LMK3H2108A19 Freuqency Configuration
OTP PageOUT0 (MHz)OUT1 (MHz)OUT2 (MHz)OUT3 (MHz)OUT4 (MHz)OUT5 (MHz)OUT6 (MHz)OUT7 (MHz)
OTP Page 0

100

100

100

100100100100100
OTP Page 1

100

100

100

100100100100100
OTP Page 2

100

100

100

100100100100100
OTP Page 3

100

100

100100100100100100
Table 1-2 LMK3H2108A19 I2C Configuration
OTP PageI2C Configuration
OTP Page 0

I2C Address: 0x09

I Byte Register Addressing

OTP Page 1

I2C Address: 0x09

I Byte Register Addressing

OTP Page 2

I2C Address: 0x09

I Byte Register Addressing

OTP Page 3

I2C Address: 0x09

I Byte Register Addressing

OTP Page 0

Table 1-3 LMK3H2108A19 GPI Settings, OTP Page 0
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0

GPI

Normal

Enabled

Disabled

GPI1GPINormalEnabledDisabled
GPI2GPINormalEnabledDisabled
GPI3GPINormalEnabledDisabled
GPI4GPINormalEnabledDisabled
GPI5GPINormalEnabledDisabled
Table 1-4 LMK3H2108A19 GPIO Settings, OTP Page 0
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0

Dynamic OTP

Normal

Enabled

Disabled

GPIO1Dynamic OTP

Normal

Enabled

Disabled

GPIO2

GPI

Normal

Enabled

Disabled

GPIO3

Status Output

Inverted

Disabled

Enabled

GPIO4

Global OE

Inverted

Disabled

Enabled

Table 1-5 LMK3H2108A19 Input Settings, OTP Page 0
InputPowered Up/DownInput FormatInput Termination
IN_0

Powered Down

N/A (IN0 Unused)

None, DC

IN_1Powered DownN/A (IN0 Unused)None, DC
IN_2Powered DownN/A (IN0 Unused)None, DC
Table 1-6 LMK3H2108A19 Output Settings, OTP Page 0
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT0

100

85 Ω LP-HCSL

PATH1

Enabled

Global OE Only

Disabled

OUT1

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled
OUT2

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled
OUT3

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled
OUT4

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled
OUT5

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled
OUT6

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled
OUT7

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled

OTP Page 1

Table 1-7 LMK3H2108A19 GPI Settings, OTP Page 1
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0

GPI

Normal

Enabled

Disabled

GPI1GPINormalEnabledDisabled
GPI2GPINormalEnabledDisabled
GPI3GPINormalEnabledDisabled
GPI4GPINormalEnabledDisabled
GPI5GPINormalEnabledDisabled
Table 1-8 LMK3H2108A19 GPIO Settings, OTP Page 1
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0

Dynamic OTP

Normal

Enabled

Disabled

GPIO1Dynamic OTP

Normal

Enabled

Disabled

GPIO2

GPI

Normal

Enabled

Disabled

GPIO3

Status Output

Inverted

Disabled

Enabled

GPIO4

Global OE

Inverted

Disabled

Enabled

Table 1-9 LMK3H2108A19 Input Settings, OTP Page 1
InputPowered Up/DownInput FormatInput Termination
IN_0

Powered Down

N/A (IN0 Unused)

None, DC

IN_1Powered DownN/A (IN0 Unused)None, DC
IN_2Powered DownN/A (IN0 Unused)None, DC
Table 1-10 LMK3H2108A19 Output Settings, OTP Page 1
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT0

100

85 Ω LP-HCSL

PATH1

Enabled

Global OE Only

Enabled, -0.25% Down-spread

OUT1

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread
OUT2

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT3

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread
OUT4

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread
OUT5

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread
OUT6

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread
OUT7

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread

OTP Page 2

Table 1-11 LMK3H2108A19 GPI Settings, OTP Page 2
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0

GPI

Normal

Enabled

Disabled

GPI1GPINormalEnabledDisabled
GPI2GPINormalEnabledDisabled
GPI3GPINormalEnabledDisabled
GPI4GPINormalEnabledDisabled
GPI5GPINormalEnabledDisabled
Table 1-12 LMK3H2108A19 GPIO Settings, OTP Page 2
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0

Dynamic OTP

Normal

Enabled

Disabled

GPIO1Dynamic OTP

Normal

Enabled

Disabled

GPIO2

GPI

Normal

Enabled

Disabled

GPIO3

Status Output

Inverted

Disabled

Enabled

GPIO4

Global OE

Inverted

Disabled

Enabled

Table 1-13 LMK3H2108A19 Input Settings, OTP Page 2
InputPowered Up/DownInput FormatInput Termination
IN_0

Powered Down

N/A (IN0 Unused)

None, DC

IN_1Powered DownN/A (IN0 Unused)None, DC
IN_2Powered DownN/A (IN0 Unused)None, DC
Table 1-14 LMK3H2108A19 Output Settings, OTP Page 2
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT0

100

85 Ω LP-HCSL

PATH1

Enabled

Global OE Only

Enabled, -0.3% Down-spread

OUT1

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.3% Down-spread
OUT2

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.3% Down-spread
OUT3

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.3% Down-spread
OUT4

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.3% Down-spread
OUT5

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.3% Down-spread
OUT6

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.3% Down-spread
OUT7

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.3% Down-spread

OTP Page 3

Table 1-15 LMK3H2108A19 GPI Settings, OTP Page 3
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0

GPI

Normal

Enabled

Disabled

GPI1GPINormalEnabledDisabled
GPI2GPINormalEnabledDisabled
GPI3GPINormalEnabledDisabled
GPI4GPINormalEnabledDisabled
GPI5GPINormalEnabledDisabled
Table 1-16 LMK3H2108A19 GPIO Settings, OTP Page 3
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0

Dynamic OTP

Normal

Enabled

Disabled

GPIO1Dynamic OTP

Normal

Enabled

Disabled

GPIO2

GPI

Normal

Enabled

Disabled

GPIO3

Status Output

Inverted

Disabled

Enabled

GPIO4

Global OE

Inverted

Disabled

Enabled

Table 1-17 LMK3H2108A19 Input Settings, OTP Page 3
InputPowered Up/DownInput FormatInput Termination
IN_0

Powered Down

N/A (IN0 Unused)

None, DC

IN_1Powered DownN/A (IN0 Unused)None, DC
IN_2Powered DownN/A (IN0 Unused)None, DC
Table 1-18 LMK3H2108A19 Output Settings, OTP Page 3
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT0

100

85 Ω LP-HCSL

PATH1

Enabled

Global OE Only

Enabled, -0.5% Down-spread

OUT1

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT2

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT3

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT4

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT5

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT6

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT7

100

85 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread