Product details

Number of outputs 8 Output type LP-HCSL, LVCMOS, LVDS Output frequency (max) (MHz) 400 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 105 Features I2C, One-Time Programmable (OTP) memory, PCIe Gen 1 - 7 compliant, Pin programmable, Serial interface Rating Catalog
Number of outputs 8 Output type LP-HCSL, LVCMOS, LVDS Output frequency (max) (MHz) 400 Core supply voltage (V) 1.8, 2.5, 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Operating temperature range (°C) -40 to 105 Features I2C, One-Time Programmable (OTP) memory, PCIe Gen 1 - 7 compliant, Pin programmable, Serial interface Rating Catalog
VQFN (RKP) 40 25 mm² 5 x 5
  • Integrated BAW resonator
    • No need for external XTAL/XO
  • Flexible output frequency
    • 2 fraction output dividers (FOD), individual channel dividers
    • Up to 400MHz output frequency
  • Flexible output format
    • 1.2/1.8/2.5/3.3V LVCMOS
    • DC- or AC-coupled LVDS
    • LP-HCSL with programmable swing. LVPECL, CML and other formats can be derived from LP-HCSL
  • Very low jitter
    • 61fs max PCIe Gen 5 CC with SSC jitter
    • 36.4fs max PCIe Gen 6 CC with SSC jitter
    • 25.5fs max PCIe Gen 7 CC with SSC jitter
  • PCIe Gen 1 to Gen 7 compliant
  • Configurable SSC
    • Programmable -0.05% to -3% down spread and ±0.025% to ±1.5% center spread, or preset -0.1%, -0.25%, -0.3% and -0.5% down spread
  • 3 inputs (LMK3H2108) or 1 input (LMK3H2104) that can be bypassed to any output
  • 5ms max startup time
  • Fail-safe input pins can be pulled high when device power is off
  • Flexible power supply
    • Each VDD pin can be independently connected to = 1.8, 2.5 or 3.3V
    • Each VDDO pin can be independently connected set to 1.8, 2.5 or 3.3V
  • -40 to 105°C ambient temperature
  • Integrated BAW resonator
    • No need for external XTAL/XO
  • Flexible output frequency
    • 2 fraction output dividers (FOD), individual channel dividers
    • Up to 400MHz output frequency
  • Flexible output format
    • 1.2/1.8/2.5/3.3V LVCMOS
    • DC- or AC-coupled LVDS
    • LP-HCSL with programmable swing. LVPECL, CML and other formats can be derived from LP-HCSL
  • Very low jitter
    • 61fs max PCIe Gen 5 CC with SSC jitter
    • 36.4fs max PCIe Gen 6 CC with SSC jitter
    • 25.5fs max PCIe Gen 7 CC with SSC jitter
  • PCIe Gen 1 to Gen 7 compliant
  • Configurable SSC
    • Programmable -0.05% to -3% down spread and ±0.025% to ±1.5% center spread, or preset -0.1%, -0.25%, -0.3% and -0.5% down spread
  • 3 inputs (LMK3H2108) or 1 input (LMK3H2104) that can be bypassed to any output
  • 5ms max startup time
  • Fail-safe input pins can be pulled high when device power is off
  • Flexible power supply
    • Each VDD pin can be independently connected to = 1.8, 2.5 or 3.3V
    • Each VDDO pin can be independently connected set to 1.8, 2.5 or 3.3V
  • -40 to 105°C ambient temperature

LMK3H2104 and LMK3H2108 are BAW-based clock generators that do not require any external XTAL or XO. The devices can be used as PCIe clock generators or general purpose clock generators. The 2 FODs (Fractional Output Divider) provide frequency flexibility, low power and low jitter at the same time.

LMK3H2104 has up to 4 differential outputs plus 2 LVCMOS outputs or up to 10 LVCMOS outputs. LMK3H2108 has up to 8 differential outputs or 16 LVCMOS outputs.

LMK3H2104 has one clock input and LMK3H2108 has three clock inputs. The clock inputs provide clock multiplexing and buffering ability. Each output bank can independently select any clock source.

The GPI and GPIO pins provide additional control flexibility. These pins can be configured as individual OE, grouped OE, I2C address selection, OTP page selection, PWRGD/PWRDN#, status output and other functions.

The device supports one-time programmable (OTP) non-volatile memory which can be customized and factory preprogrammed.

LMK3H2104 and LMK3H2108 are BAW-based clock generators that do not require any external XTAL or XO. The devices can be used as PCIe clock generators or general purpose clock generators. The 2 FODs (Fractional Output Divider) provide frequency flexibility, low power and low jitter at the same time.

LMK3H2104 has up to 4 differential outputs plus 2 LVCMOS outputs or up to 10 LVCMOS outputs. LMK3H2108 has up to 8 differential outputs or 16 LVCMOS outputs.

LMK3H2104 has one clock input and LMK3H2108 has three clock inputs. The clock inputs provide clock multiplexing and buffering ability. Each output bank can independently select any clock source.

The GPI and GPIO pins provide additional control flexibility. These pins can be configured as individual OE, grouped OE, I2C address selection, OTP page selection, PWRGD/PWRDN#, status output and other functions.

The device supports one-time programmable (OTP) non-volatile memory which can be customized and factory preprogrammed.

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Technical documentation

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* Data sheet LMK3H2104 and LMK3H2108 4- or 8-Output PCIe Gen 1-6 Compliant Low jitter General Purpose BAW Clock Generator datasheet (Rev. A) 30 Oct 2025
User guide LMK3H2108A19 Register Map PDF | HTML 23 Jan 2026
User guide LMK3H2108A19 Configuration Guide PDF | HTML 22 Jan 2026
User guide LMK3H2108 Configuration Summary PDF | HTML 08 Dec 2025
User guide LMK3H2108A11 Configuration Guide PDF | HTML 08 Dec 2025
User guide LMK3H2108A11 Register Map PDF | HTML 08 Dec 2025
User guide LMK3H2108A16 Configuration Guide PDF | HTML 08 Dec 2025
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User guide LMK3H2108A0F Register Map PDF | HTML 24 Nov 2025
User guide LMK3H2108A14 Configuration Guide PDF | HTML 24 Nov 2025
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User guide LMK3H2108A15 Configuration Guide PDF | HTML 24 Nov 2025
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User guide LMK3H2108A0F Configuration Guide PDF | HTML 20 Nov 2025
User guide LMK3H2108A01 Configuration Guide PDF | HTML 18 Nov 2025
User guide LMK3H2108A03 Configuration Guide PDF | HTML 17 Nov 2025
User guide LMK3H2108A03 Register Map PDF | HTML 17 Nov 2025
User guide LMK3H2108A04 Configuration Guide PDF | HTML 17 Nov 2025
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User guide LMK3H2108A0D Configuration Guide PDF | HTML 17 Nov 2025
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User guide LMK3H2108 Register Map PDF | HTML 21 Aug 2025

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Application software & framework

LMK3H2108-DESIGN LMK3H210x configuration GUI software

Software provides configuration support for LMK3H2104 and LMK3H2108 devices
Supported products & hardware

Supported products & hardware

Application software & framework

LMK3H2108-GUI Programming GUI for the public release of the LMK3H2108 devices.

The TICS Pro 2 software is required for interfacing with the LMK3H210x family of devices. This allows for handling of the register paging functionality automatically.
Supported products & hardware

Supported products & hardware

Simulation model

LMK3H210X IBIS Model

SNAM304.ZIP (291 KB) - IBIS Model
Design tool

PLLATINUMSIM-SW PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware

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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RKP) 40 Ultra Librarian

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