SLVAFQ2 December   2023 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Delivery Networks (PDNs)
    1. 2.1 TPS652190C Power Rails Configuration
    2. 2.2 LP87334F Power Rails Configuration
    3. 2.3 Powering i.MX 8M Plus and DDR4
    4. 2.4 Powering i.MX 8M Plus and LDDR4
    5. 2.5 PMICs Digital Configuration
    6. 2.6 Power-Up Sequence
    7. 2.7 Power-Down Sequence
  6. 3Supporting i.MX 8M Plus Low Power Modes
  7. 4PMIC Schematic Example
  8. 5TPS6521905 User-Programmable Version
  9. 6Summary
  10. 7References

2 Power Delivery Networks (PDNs)

This section details how the TPS652190C and LP87334F power resources are connected to the processor voltage domains and peripherals. All the i.MX 8M Plus power domains except VDD_SOC are supplied by the primary PMIC (TPS65219). The secondary PMIC (LP8733) can be replaced with an external 0.85V Buck regulator if preferred. Some of the external peripherals like uSD card and Ethernet PHY are optional and might not be needed for the end product. These peripherals are included in the PDN as an example. The reference PDN has a 3.3 V input supply and uses an external 3.3 V power-switch to connects the 3.3 V pre-regulator to the processor 3.3 V IO voltage domain. All the PMIC rails, except the ones configured as load-switch or bypass, can be supplied by either 5 V or 3.3 V.

Note: TPS652190C is a factory programmed device and TPS6521905 is the user-programmable version.