3 Configuring the TPS55288 Buck-Boost Converter Through I2C3

For the TPS55288, the goal is to program the converter output behavior based on PD negotiations, and to maintain safe defaults at power-up and disconnect. The TPS65992S event table (indices 0–8 allocated to TPS55288) is set up accordingly. Key register settings on the TPS55288 are derived from the data sheet:

• REF (0x00/0x01): Sets the internal reference voltage which, in conjunction with the feedback configuration, determines V_OUT. This is a 10-bit value split across two registers (0x01 is MSB, 0x00 is LSB). One LSB corresponds to about 1.129mV of reference voltage. By adjusting REF, the output can be changed from a minimum of about 45mV reference (0x0000, yields the lowest output) up to 1.2V reference (0x03FF, yields maximum output). The default REF value after reset is 0x00D2 (LSB=0xD2, MSB=0x00), which corresponds to about 282mV. The TPS55288 default feedback ratio is set for internal sensing (see V_OUT_FS below), so 282mV reference results in approximately 5V at the output (more on this below).
• V_OUT_FS (0x04): The Feedback Selection register controls whether the converter uses an internal resistor divider for V_OUT sensing or an external feedback network. The feedback selection register selects the internal feedback ratio if used. By default, V_OUT_FS = 0x03 (binary 0000_0011), which means internal feedback enabled (bit7 = 0) and the internal feedback ratio set to 0.0564 (bits1:0 = 11b). A ratio of 0.0564 corresponds to a 20× gain from the reference to the output (since 0.0564 × 20 ≈ 1), allowing the output to reach about 20V when the reference is at the maximum of about 1.129V. In simpler terms, with the default ratio, a 282mV reference yields about 5V output, and a 1.129V reference yields about 20V output, establishing the range needed for PD profiles.
• MODE (0x06): The Mode Control register contains various control bits; notably bit7 is OE (Output Enable), which must be set to 1 to turn on the converter output. Other bits configure features like hiccup protection, discharge on shutdown, I2C address selection, and light-load mode (PFM/FPWM). Of interest, bit2 (I2CADD) selects the I2C address (0 for 0x74, 1 for 0x75), and bit0 (MODE) selects whether certain settings are taken from external resistors or internal registers. In our design, we leave I2CADD = 0 (using 0x74 address) and use the default control method for VCC and PFM (external resistor control, bit0 = 0), since the hardware design provides the proper defaults. We, however, enable the output (OE) through I2C and verify other bits are appropriately set for operation.

Using these registers, the TPS65992S I2C event sequences are configured as follows:

Power-On Initialization

On a Power-On Reset (PoR) of the PD controller, we initialize the TPS55288 to a known safe state so that the PD controller is ready to supply 5V by default (the standard USB-C default voltage) once the port is active. The TPS65992S firmware triggers several I2C writes to the TPS55288 immediately after PD controller reset:

• Set Reference Voltage: Write 0xD2 to TPS55288 register 0x00 (LSB of REF). This, combined with the default MSB (0x00), sets the REF value to 0x00D2. As noted above, 0x00D2 corresponds to about 282mV reference, which (with the default feedback ratio) equates to about 5V output. This effectively programs the converter for 5V output as a starting point.
• Set Feedback Configuration: Write 0x03 to register 0x04 (VOUT_FS). This explicitly verifies that the converter uses the internal feedback network and the 0.0564 ratio (which is the default reset state). Writing 0x03 here is mainly for completeness – this confirms the feedback mode in case any non-default configuration was latched or to guard against any uncertainty at start-up. This keeps the internal feedback enabled and selects the ratio that allows the full PD voltage range (up to 20V) through internal scaling.
• Enable Converter Output: Write 0xA0 to register 0x06 (MODE). This sets bit7 (OE) = 1 to turn on the output, and also has bit5 = 1 (keeping hiccup mode enabled as default). The value 0xA0 (binary 1010_0000) essentially flips OE to 1 while leaving other bits at the desired values (for instance, 0x20 was the reset value with OE=0, HICCUP=1, and so on, and 0xA0 changes OE to 1). After this write, the TPS55288 is enabled and regulating to about 5V output.

These three writes (to 0x00, 0x04, 0x06) are done in sequence during the PD controller initialization. By configuring the power converter at PoR, the design maintains that even before any USB-C connection is made, the TPS55288 comes up in a default 5V standby output state (or ready to provide 5V when enabled). This is important for compliance with the USB-C standard which requires 5V present on VBUS initially for attachment. In our case, the actual enabling of VBUS to the connector is controlled by the PD controller power-path switch, but the TPS55288 output is set to the correct level and turned on internally.

(The exact numeric values chosen – 0xD2, 0x03, 0xA0 – correspond to the desired start-up configuration as derived from the TPS55288 data sheet. 0xD2 (210 decimal) for REF LSB is the code for about 5V as explained, 0x03 for VOUT_FS selects internal feedback with 0.0564 ratio, and 0xA0 enables output. Designers can refer to the TPS55288 Register Maps in the data sheet for detailed bit definitions.)

Dynamic PDO Voltage Adjustment (Source PDO Negotiation)

With the converter initialized, the PD controller next needs to adjust the TPS55288 output each time a new PD contract is negotiated. The TPS65992S is configured to issue I2C writes to the REF register whenever a Source PDO is selected by the connected device (for example, whenever the PD source voltage changes). In our example, suppose the system offers four fixed PDOs at 5V, 9V, 15V, and 20V. We define four event triggers in the TPS65992S firmware. (For example, SRC_PDO1_NEGOTIATED, SRC_PDO2_NEGOTIATED, and so on), each mapped to writing the appropriate value to the TPS55288 REF registers.

• 5V Contract (PDO1): Write 0xD2 0x00 to TPS55288 register 0x00. This is a two-byte write (0x00 is the starting register for REF LSB). The data bytes 0xD2 0x00 set REF = 0x00D2 (LSB=D2h, MSB=00h) which, as discussed, corresponds to about 5.0V output. (In the PD tool, Data Length=3 for this entry: 1 byte for reg address + 2 data bytes.)
• 9V Contract (PDO2): Write 0x9A 0x01 to register 0x00 (two-byte data, setting REF = 0x019A). In the TPS55288 internal DAC code, 0x019A corresponds to roughly 9V. Specifically, 0x019A = 410 decimal; 410 × 1.129mV ≈ 463mV reference. With 0.0564 feedback ratio, this yields V_OUT ≈ 463mV / 0.0564 ≈ 8.21V. However, the converter output slightly overshoots to meet 9V at load (the exact values are chosen based on calibration and experimentation). According to typical settings, 0x019A is the code used for 9V in this design.
• 15V Contract (PDO3): Write 0xC5 0x02 to register 0x00 (REF = 0x02C5). 0x02C5 = 709 decimal; 709 × 1.129mV ≈ 800mV reference. Divided by 0.0564, this yields about 14.2V. Again, the code is selected to produce approximately 15V under expected conditions (taking into account load and converter tolerance).
• 20V Contract (PDO4): Write 0xBF 0x03 to register 0x00 (REF = 0x03BF). 0x03BF = 959 decimal; 959 × 1.129mV ≈ 1.083V reference. With the 0.0564 ratio, this gives about 19.2V. This is intended to hit about 20V at no-load or nominal load (the TPS55288 feedback and reference may be trimmed such that 0x03C0 might overshoot slightly above 20V, so 0x03BF is used to stay at or just below 20V typical). Essentially, 0x03BF is the calibrated code for 20V_in our setup.

Each of these writes targets the TPS55288 REF registers to dynamically change V_OUT on the fly. The PD controller issues the appropriate command immediately after the PD contract is established. This way, as soon as a sink requests a higher voltage (for example, 15V), the TPS65992S writes the new REF value and the TPS55288 slews the output to the requested level. The slew rate of the output can be controlled by the TPS55288 VOUT_SR register (0x03) if needed, but in our design we rely on the converter default slew, which is typically configured to meet PD timing requirements.

Detach and Reset Behavior

When the USB-C cable is unplugged or the sink device is detached, return the power supply to a safe state. Write 0xD2 0x00 to registers 0x00 (LSB) and 0x01 (MSB). This two-byte write fully resets the reference voltage to the desired 5V default setting, eliminating the possibility of residual high-voltage conditions. Regardless, the outcome is that the TPS55288 output drops to a safe level (approximately 5V or below) when a disconnect occurs. This prevents any residual high voltage on VBUS after the cable is removed.

By setting up these I2C command events for the TPS55288, all power supply adjustments are automated by the TPS65992S firmware without the need for any external MCU intervention. The PD controller monitors the USB-C state and PD messages and triggers the appropriate pre-programmed I2C writes. This maintains that as PD contracts change, the converter seamlessly provides the requested voltage, and when no contract is active (detach or idle), the converter is in a known default state.