SLVAFY6A November   2025  – May 2026 TPS26742E-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Purpose and Scope
  5. 2Application Firmware Image Bundle
  6. 3TFU Programming the TPS2674x-Q1
    1. 3.1 Programming Over I2C1
      1. 3.1.1 Configuration of I2C1
      2. 3.1.2 I2C1 Hardware Connection Using the TPS26742EQ1EVM
      3. 3.1.3 I2C1 Hardware Connection Using the TPS26744EQ1EVM
    2. 3.2 Programming Over I2C4
      1. 3.2.1 Configuration of I2C4
      2. 3.2.2 I2C4 Hardware Connection Using the TI-PD-ANALYZER
      3. 3.2.3 Using the TI-PD-ANALYZER
  7. 4Custom Designing a TFU Programmer
  8. 5Summary
  9. 6Revision History

3.2.1 Configuration of I2C4

Programming the integrated flash memory through the TPS2674x-Q1 I2C4 interface requires the use of the following pins:

  • 28: DBG_SCL/PA_DM (P1_GPO8)
  • 29: DBG_SDA/PA_DP (P1_GPO7)
  • 5: GND

The I2C requirements and CMOS logic level specifications are found in the Electrical Characteristics of the TPS2674x-Q1 data sheet.

The DBG_SCL (P1_GPO8) and DBG_SDA (P1_GPO7) pins provide access to the internal I2C4 interface. See Figure 3-5.

Internal Connection to I2C4 Figure 3-5 Internal Connection to I2C4