3 Solutions for Test Mode and Measured Waveforms

From the analysis of test modes above, if the first test mode is entered, it can be avoided by modifying the control logic, that is, inserting a 6ms 0:0 at IN1 and IN2 to exit the test mode to avoid restart; if the second test mode is entered, it can only be exited by power cycling, which is unacceptable in many practical applications. Finally, TI decided on the roadmap planning for DRV8231 and derivatives such as DRV8251/DRV8870, and made the following optimizations for test modes.

1. Regarding the entry method, since previously ns-level glitch greater than 7.5V would cause the DRV8231 to enter test modes, TI added deglitch circuits inside IN1 and IN2 to improve anti-interference capability. Therefore, when glitch time < 1.9us, the DRV8231 will not enter test modes. The comparison test is as follows: As shown in Figure 3-1, after adding the deglitch circuit internally, applying 10V on IN2 for 1.8us did not cause the chip to enter test modes; as shown in Figure 3-2, applying 10V on IN2 for 2us caused the DRV8231 to enter the second test mode, with OUT1 and OUT2 outputting high level simultaneously.
   Figure 3-1 Test Mode Not Entered with 1.8us 10V IN2
   Figure 3-2 Test Mode Entered with 2us 10V IN2
2. Regarding the exit method, even if the DRV8231 receives glitch >1.9us and enters the second test mode, as long as IN1 and IN2 are restored to the normal 5V level, the DRV8231 can exit from the test mode. As shown in Figure 3-3, when IN2 increases from 5V to 10V, the DRV8231 enters the second test mode, with OUT1 and OUT2 reaching high level simultaneously; as shown in Figure 3-4, when IN2 recovers from 10V to 5V, the DRV8231 exits the test mode, with OUT1 high and OUT2 low, and the BDC motor operates normally.