SLVK158 November   2023 TPS7H6003-SP

PRODUCTION DATA  

  1.   1
  2.   TPS7H6003-SP Single-Event Effects (SEE)
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects (SEE)
  6. 3 Device and Test Board Information
  7. 4 Irradiation Facility and Setup
  8. 5 Depth, Range, and LETEFF Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. 8 Single-Event Transients (SET)
  12. 9 Event Rate Calculations
  13. 10Summary
  14.   A References

2 Single-Event Effects (SEE)

SEE testing was performed on an evaluation board designed for testing the TPS7H6003-SP under heavy-ion radiation. The board was powered up in different input and output conditions at Texas A&M University to cover the spectrum of destructive SEE (DSEE) and Single-Event Transients (SET). The devices were tested at the TAMU Cyclotron Radiation Effects Facility using a superconducting cyclotron and an advanced electron cyclotron resonance (ECR) ion source. DSEE testing included Single-Event Latch-up (SEL), Single-Event Burnout (SEB), and Single-Event Gate Rupture (SEGR). In mixed technologies such as the BiCMOS process used on the TPS7H6003-SP, the CMOS circuitry introduces a potential for SEL susceptibility.

SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts) [1,2]. The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is “latched”) until power is removed, the device is reset, or until the device is destroyed by the high-current state. The TPS7H6003-SP was tested for SEL at the maximum recommended input voltage (VIN) of 14-V and the maximum recommended boot voltage (VBOOT) of 14-V. The ASW (High-Side Driver Signal Return) was set to 150-V. Three different operation modes were tested during SEL testing. The first mode was PWM mode with the EN (HI) and PWM (LI) inputs in the following configuration:

  • EN/HI:
    • 14-V DC signal (SEL)
  • PWM/LI:
    • 14-V square wave switching at 500 kHz, 1 MHz, and 2 MHz (SEL)

The second and third modes of operation were IIMEN (where the optional interlock protection is enabled) and IIMDIS (where the optional interlock protection is disabled) mode (for the IIM modes there are static (IIMST) and switching (IIMSW) cases) in which EN (HI) and PWM (LI) were configured in the following manner (both cases were tested under the same conditions):

  • Case 1 - EN/HI = 0 V, PWM/LI = 14 V (Static SEL)
  • Case 2 - EN/HI = 14 V, PWM/LI = 0 V (Static SEL)
  • Case 3- EN/HI and PWM/LI = 14 V square wave switching at 500-kHz offset by 180° (Switching SEL)

During testing of the four devices, the TPS7H6003-SP did not exhibit any SEL with heavy-ions with LETEFF = 75 MeV × cm2 / mg at flux of approximately 105 ions / cm2 × s, fluence of approximately 107 ions / cm2, and a die temperature of 125°C.

The primary concern for SEB and SEGR was the power LDMOS of this device. Because of this, SEB/SEGR was evaluated up to the maximum VIN and VBOOT in both IIM and PWM mode. In IIM mode the TPS7H6003-SP was also tested in the “Off” case in which both EN/HI and PWM/LI = 0 V to determine if either of the outputs incorrectly turned on when the outputs must not have during heavy-ion radiation. Because it has been shown that the MOSFET susceptibility to burnout decrements with temperature [5], the device was evaluated while operating under room temperatures. The specific test conditions the device was tested are as follows:

PWM Mode:

  • EN/HI:
    • 14-V DC signal (SEBON)
    • 0-V DC signal (SEBOFF)

  • PWM/LI:

    • 14-V Square Wave switching at 500-kHz, 1 MHz, and 2 MHz (SEBON)
    • 0-V DC signal (SEBOFF)

IIM Modes:

  • Case 1- EN/HI = 0-V, PWM/LI = 14 V (Static SEBON)
  • Case 2 - EN/HI = 14-V, PWM/LI = 0 V (Static SEBON)
  • Case 3 - EN/HI = 0-V, PWM/LI = 0 V (SEBOFF)
  • Case 4 - EN/HI & PWM/LI = 14-V square wave switching at 500-kHz offset by 180° (Switching SEBON)

During the SEB/SEGR testing, not a single input current event was observed, demonstrating that the TPS7H6003-SP is SEB/SEGR-free up to LETEFF = 75 MeV × cm2 / mg at a flux of approximately 105 ions / cm2 × s, fluences of approximately 107 ions / cm2, and a die temperature of ≈25°C.

The TPS7H6003-SP was characterized for SET with LETEFF = 48 to 75 MeV × cm2 / mg at flux ≈105 ions / cm2 × s, fluence of ≈107 ions / cm2, and a die temperature of 25°C. For SET the device operated at nominal operating conditions with a VIN of 12 V and VBOOT of 12 V with ASW at 150 V. The specific test conditions for the devices for SET are as follows:

PWM Mode:

  • EN/HI:
  • 5-V DC signal (SET)

PWM/LI:

  • 5-V Square Wave switching at 500-kHz and 50% duty cycle (SET)

IIM Modes:

  • Case 1 – EN/HI = 0-V, PWM/LI = 5-V (Static SET)
  • Case 2 – EN/HI = 5-V, PWM/LI = 0-V (Static SET)
  • Case 3 - EN/HI & PWM/LI = 5-V square wave switching at 500-kHz offset by 180° (Switching SET)

Under these conditions the device showed on SET signature which was self-recoverable without the need for external intervention in both PWM and IIM mode. In PWM mode and IIMSW mode HO and LO were monitored to see if the output pulse width ever exceeded a 20 % trigger. In IIMST mode HO and LO were monitored to see if the signals triggered on either a positive or negative edge depending on whether HO or LO were forced high based on the input value on EN/HI and PWM/LI. In all cases transients lasted approximately 5 us before recovering back to normal operation. Transients are further discussed in the Single-Event Transients section. To see the SET results of the TPS7H6003-SP, see Single-Event Transients (SET).