SLVK230 November   2025 TPS7H4102-SEP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects (SEE)
  6. 3 Device and Test Board Information
  7. 4 Irradiation Facility and Setup
  8. 5 LETEFF and Range Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Safe Operating Area (SOA) Results
    2. 7.2 Single-Event Latch-up (SEL) Results
    3. 7.3 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. 8 Single-Event Transients (SET)
  12. 9 Event Rate Calculations
  13. 10Summary
  14.   A References

3 Device and Test Board Information

The TPS7H4102-SEP is packaged in a 64-pin plastic package as shown in Figure 3-1. The TPS7H4102EVM was used to evaluate the performance and characteristics of the TPS7H4102-SEP under heavy ion radiation. The TPS7H4102EVM is shown in Figure 3-2. The schematic is shown in Figure 3-3. For further detail please reference the TPS7H4102EVM User's Guide.

Photograph of Delidded TPS7H4102-SEP [Left] and Pinout Diagram [Right]Figure 3-1 Photograph of Delidded TPS7H4102-SEP [Left] and Pinout Diagram [Right]
Note: The package was delidded/decapped to reveal the die face for all heavy-ion testing.
TPS7H4102-SEP EVM Top ViewFigure 3-2 TPS7H4102-SEP EVM Top View

Note for the VOUT=1.2V case both outputs were configured similar to VOUT1 and for the VOUT=1.8V case both outputs were configured similar to VOUT4. Please refer to Table 6-2 for a breakdown of component values.

TPS7H4102-SEP EVM SchematicsFigure 3-3 TPS7H4102-SEP EVM Schematics