SLVSAC3D May   2011  – December 2014 TPS62730 , TPS62732 , TPS62733

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 DCS-Control™
      2. 9.3.2 ON/BYP Mode Selection
      3. 9.3.3 STAT Open-Drain Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start-Up
      2. 9.4.2 Automatic Transition from DC-DC to Bypass Operation
      3. 9.4.3 Internal Current Limit
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Output Filter Design (Inductor and Output Capacitor)
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 DC-DC Output Capacitor Selection
        4. 10.2.2.4 Additional Decoupling Capacitors
        5. 10.2.2.5 Input Capacitor Selection
          1. 10.2.2.5.1 Input Buffer Capacitor Selection
        6. 10.2.2.6 Checking Loop Stability
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

7 Pin Configuration and Functions

DRY Package
6 Pins
Top View
po_lvsac3.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO
VIN 3 PWR VIN power supply pin. Connect this pin close to the VIN terminal of the input capacitor. A ceramic capacitor of 2.2 µF is required.
GND 4 PWR GND supply pin. Connect this pin close to the GND terminal of the input and output capacitor.
ON/BYP 5 IN This is the mode selection pin of the device. Pulling this pin to low forces the device into ultra low-power bypass mode. The output of the DC-DC converter is connected to VIN through an internal bypass switch. Pulling this pin to high enables the DC-DC converter operation. This pin must be terminated and is controlled by the system.
SW 2 OUT This is the switch pin and is connected to the internal MOSFET switches. Connect the inductor to this terminal.
VOUT 6 IN Feedback Pin for the internal feedback divider network and regulation loop. The internal bypass switch is connected between this pin and VIN. Connect this pin directly to the output capacitor with short trace.
STAT 1 OUT This is the open-drain status output with active low level. An internal comparator drives this output. The pin is high impedance with ON/BYP = low. With ON/BYP set to high the device and the internal VOUT comparator becomes active. The active low STAT pin indicates if the DC-DC regulator is settled and the output voltage above the VTSTAT threshold. If not used, this pin can be left open.