SLVSB56C May   2012  – February 2014 TPS54160 , TPS54160A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Terminal Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation Output Current
      3. 8.3.3  Pulse Skip Eco-mode
      4. 8.3.4  Bootstrap Voltage (BOOT)
      5. 8.3.5  Low Dropout Operation
      6. 8.3.6  Error Amplifier
      7. 8.3.7  Voltage Reference
      8. 8.3.8  Adjusting the Output Voltage
      9. 8.3.9  Enable and Adjusting Undervoltage Lockout
      10. 8.3.10 Slow Start and Tracking Pin (SS/TR)
      11. 8.3.11 Overload Recovery Circuit
      12. 8.3.12 Sequencing
      13. 8.3.13 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      14. 8.3.14 Overcurrent Protection and Frequency Shift
      15. 8.3.15 Selecting the Switching Frequency
      16. 8.3.16 How to Interface to RT/CLK Pin
      17. 8.3.17 Power Good (PWRGD Pin)
      18. 8.3.18 Overvoltage Transient Protection
      19. 8.3.19 Thermal Shutdown
      20. 8.3.20 Small Signal Model for Loop Response
      21. 8.3.21 Simple Small Signal Model for Peak Current Mode Control
      22. 8.3.22 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with VIN < 3.5 V (Minimum VIN)
      2. 8.4.2 Operation with EN Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1  Selecting the Switching Frequency
        2. 9.2.2.2  Output Inductor Selection (LO)
        3. 9.2.2.3  Output Capacitor
        4. 9.2.2.4  Catch Diode
        5. 9.2.2.5  Input Capacitor
        6. 9.2.2.6  Slow Start Capacitor
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  Under Voltage Lock Out Set Point
        9. 9.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 9.2.2.10 Compensation
        11. 9.2.2.11 Power Dissipation Estimate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

Over operating temperature range (unless otherwise noted).
VALUE UNIT
MIN MAX
Input voltage VIN –0.3 65 V
EN(2) –0.3 5
BOOT 73
VSENSE –0.3 3
COMP –0.3 3
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 3.6
Output voltage BOOT-PH 8 V
PH –0.6 65
PH, 10-ns Transient –2 65
Voltage Difference PAD to GND ±200 mV
Source current EN 100 μA
BOOT 100 mA
VSENSE 10 μA
PH Current Limit A
RT/CLK 100 μA
Sink current VIN Current Limit A
COMP 100 μA
PWRGD 10 mA
SS/TR 200 μA
Operating junction temperature –40 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See the Enable and Adjusting Undervoltage Lockout section of this data sheet for details.

7.2 Handling Ratings

MIN MAX UNIT
TSTG Storage temperature –65 150 °C
VESD(1) Human Body Model (HBM) ESD Stress Voltage (2)
QSS 009-105 (JESD22-A114A)		 TPS54160 1 kV
Human Body Model (HBM) ESD Stress Voltage (2)
QSS 009-105 (JESD22-A114A)		 TPS54160A 2 kV
Charged Device Model (CDM) ESD Stress Voltage (3)
QSS 009-147 (JESD22-C101B.01)		 500 V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Supply input voltage range 3.5 60 V
VO Output voltage range 0.8 58 V
IO Output current range 0 1.5 A
TJ Junction Temperature –40 150 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS54160
TPS54160A		 UNITS
DGQ (10 PINS) DRC (10 PINS)
θJA Junction-to-ambient thermal resistance (standard board) 62.5 40 °C/W
θJCtop Junction-to-case (top) thermal resistance 83 65
θJB Junction-to-board thermal resistance 28 8
ψJT Junction-to-top characterization parameter 1.7 0.6
ψJB Junction-to-board characterization parameter 20.1 7.5
θJCbot Junction-to-case (bottom) thermal resistance 21 7.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 3.5 to 60V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 3.5 60 V
Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 2.5 V
Shutdown supply current EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V 1.3 4 μA
Operating : nonswitching supply current VSENSE = 0.83 V, VIN = 12 V, 25°C 116 136
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling, 25°C (TPS54160) 0.9 1.25 1.55 V
No voltage hysteresis, rising and falling (TPS54160A) 1.11 1.25 1.36 V
Input current Enable threshold +50 mV –3.8 μA
Enable threshold –50 mV –0.9
Hysteresis current 1.91 2.95 3.99 μA
VOLTAGE REFERENCE
Voltage reference TJ = 25°C 0.792 0.8 0.808 V
0.784 0.8 0.816
HIGH-SIDE MOSFET
On-resistance VIN = 3.5 V, BOOT-PH = 3 V 300 mΩ
VIN = 12 V, BOOT-PH = 6 V 200 410
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gM) –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V 97 μMhos
Error amplifier transconductance (gM) during slow start –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V,
VVSENSE = 0.4 V		 26 μMhos
Error amplifier dc gain VVSENSE = 0.8 V 10,000 V/V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink V(COMP) = 1 V, 100-mV overdrive ±7 μA
COMP to switch current transconductance 6 A/V
CURRENT LIMIT
Current limit threshold VIN = 12 V, TJ = 25°C 1.8 2.7 A
THERMAL SHUTDOWN
Thermal shutdown 182 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode 100 2500 kHz
fSW Switching frequency RT = 200 kΩ 450 581 720 kHz
Switching frequency range using CLK mode 300 2200 kHz
Minimum CLK input pulse width 40 ns
RT/CLK high threshold 1.9 2.2 V
RT/CLK low threshold 0.5 0.7 V
RT/CLK falling edge to PH rising edge delay Measured at 500 kHz with RT resistor in series 60 ns
PLL lock in time Measured at 500 kHz 100 μs
SLOW START AND TRACKING (SS/TR)
Charge current VSS/TR = 0.4 V 2 μA
SS/TR-to-VSENSE matching VSS/TR = 0.4 V 45 mV
SS/TR-to-reference crossover 98% nominal 1.0 V
SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 112 μA
SS/TR discharge voltage VSENSE = 0 V 54 mV
POWER GOOD (PWRGD PIN)
VVSENSE VSENSE threshold VSENSE falling 92%
VSENSE rising 94%
VSENSE rising 109%
VSENSE falling 107%
Hysteresis VSENSE falling 2%
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA
On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Ω
Minimum VIN for defined output V(PWRGD) < 0.5 V, I(PWRGD) = 100 μA 0.95 1.5 V

7.6 Typical Characteristics

rdson_tj_lvs795.gif
Figure 1. On Resistance vs Junction Temperature
imax_tj_lvs795.gif
Figure 3. Switch Current Limit vs Junction Temperature
fs_rt_clk_lvs795.gif
Figure 5. Switching Frequency vs RT/CLK Resistance High Frequency Range
ea_tj_lvs795.gif
Figure 7. EA Transconductance During SLOW Start vs Junction Temperature
en_tj_lvs795.gif
Figure 9. EN Pin Voltage vs Junction Temperature
ic2_tj_lvs795.gif
Figure 11. EN Pin Current vs Junction Temperature
ss_tr2_tj_lvs795.gif
Figure 13. SS/TR Discharge Current vs Junction Temperature
icc_tj_lvs795.gif
Figure 15. Shutdown Supply Current vs Junction Temperature
icc2_tj_lvs795.gif
Figure 17. VIN Supply Current vs Junction Temperature
rdson2_tj_lvs795.gif
Figure 19. PWRGD On Resistance vs Junction Temperature
boot_tj_lvs795.gif
Figure 21. BOOT-PH UVLO vs Junction Temperature
offset_vs_lvs795.gif
Figure 23. SS/TR To VSENSE Offset vs VSENSE
vref_tj_lvs795.gif
Figure 2. Voltage Reference vs Junction Temperature
fs_tj_lvs795.gif
Figure 4. Switching Frequency vs Junction Temperature
C006_SLVS919.gif
Figure 6. Switching Frequency vs RT/CLK Resistance Low Frequency Range
ea2_tj_lvs795.gif
Figure 8. EA Transconductance vs Junction Temperature
ic_tj_lvs795.gif
Figure 10. EN Pin Current vs Junction Temperature
ss_tr_tj_lvs795.gif
Figure 12. SS/TR Charge Current vs Junction Temperature
fs_vsense_lvs795.gif
Figure 14. Switching Frequency vs VSENSE
icc_vi_lvs795.gif
Figure 16. Shutdown Supply Current vs Input Voltage (Vin)
icc_vi2_lvs795.gif
Figure 18. VIN Supply Current vs Input Voltage
pwrgd_tj_lvs795.gif
Figure 20. PWRGD Threshold vs Junction Temperature
uvlo_tj_lvs795.gif
Figure 22. Input Voltage (UVLO) vs Junction Temperature
offset_tj_lvs795.gif
Figure 24. SS/TR To VSENSE Offset vs Temperature