SLVSDQ0K September   2017  – September 2025 TPS7B82-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics: Grade 1 Options
    6. 5.6 Electrical Characteristics: Grade 0 Options
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Enable (EN)
      2. 6.3.2 Undervoltage Shutdown
      3. 6.3.3 Current Limit
      4. 6.3.4 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Operation With VIN Lower Than 3 V
      2. 6.4.2 Operation With VIN Larger Than 3 V
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Capacitor
        2. 7.2.2.2 Output Capacitor
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

9 Revision History

Changes from Revision J (August 2023) to Revision K (September 2025)

  • Added WSON wettable flank (DRV) package to documentGo

Changes from Revision I (September 2017) to Revision J (August 2023)

  • Changed VOUT parameter test conditions in Electrical Characteristics tableGo
  • Added Device Nomenclature sectionGo