SLVSFH3C October   2021  – August 2026 TPS631000

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Rating
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics 
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Undervoltage Lockout (UVLO)
      2. 6.3.2 Enable and Soft Start
      3. 6.3.3 Adjustable Output Voltage
      4. 6.3.4 Mode Selection (PFM/FPWM)
      5. 6.3.5 Reverse Current Operation
      6. 6.3.6 Protection Features
        1. 6.3.6.1 Input Overvoltage Protection
        2. 6.3.6.2 Output Overvoltage Protection
        3. 6.3.6.3 Short Circuit Protection
        4. 6.3.6.4 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 Inductor Selection
        3. 7.2.2.3 Output Capacitor Selection
        4. 7.2.2.4 Input Capacitor Selection
        5. 7.2.2.5 Setting the Output Voltage
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.4.1 Layout Guidelines

The PCB layout is an important step to maintain the high performance of the TPS631000.

  • Place input and output capacitors as close as possible to the IC. Traces must be kept short. Route wide and direct traces to the input and output capacitors results in low trace resistance and low parasitic inductance.
  • The sense trace connected to FB is signal trace. Keep these traces away from LX1 and LX2 nodes.