SLVSFR3B april   2022  – june 2023 TPSI2140-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dielectric Withstand Testing (HiPot)
      2. 9.2.2 Design Requirements
      3. 9.2.3 Design Procedure - Chassis Ground Reference
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Typical Application

Insulation Resistance Monitoring

In high voltage applications such as electric vehicle systems, the high voltage battery pack is intentionally isolated from the chassis domain of the car to protect the driver and prevent damage to electrical components. These systems actively monitor the integrity of this insulation to ensure the safety of the system throughout its lifetime. This active monitoring is referred to as insulation resistance monitoring (also known as isolation check, insulation check, isolation monitoring, insulation monitoring, and residual current monitoring (RCM)) and is performed by measuring the resistances from each of the battery terminals to the chassis ground, illustrated below as RISOP and RISON.

GUID-20220328-SS0I-VVWP-NZ9P-Z6HWGTQGVWTB-low.svg Figure 9-1 Insulation Resistance Model

There are multiple design architectures using the TPSI2140-Q1 to measure these insulation resistances, RISOP and RISON. Some architectures employ a microcontroller that performs measurements from the high voltage domain, which will be referred to in this document as the Battery V- Reference architecture. Others use a microcontroller in the low voltage domain, which will be referred to in this document as the Chassis Ground Reference architecture. The primary difference between the two architectures is the node that the MCU uses as its GND reference. An example of a Battery V- MCU is the BQ79631-Q1 UIR sensor.

GUID-20220328-SS0I-8RVG-PXF3-3MZGNVJ5FTPJ-low.svg Figure 9-2 Different MCU ADC Reference Examples

The two following sections demonstrate the measurement algorithms and the systems of equations used to calculate the isolation resistances using each architecture.

Battery V- Reference Example

A Battery V- Reference architecture is shown below with the TPSI2140-Q1 illustrated as a switch (SW1 and SW2). SW2 initiates a connection between the chassis and PACK- and enables the measurement path to the ADC. SW1 initiates a connection between the chassis and the PACK+. RDIV1 and RDIV2 form a divider which scales the measured voltages down to the appropriate ADC range.

GUID-DC67CD1D-61D1-4F2F-8632-69CC4FDCCEEC-low.svg Figure 9-3 Battery V- Reference Architecture

Two ADC measurements must be taken in order to obtain enough information to calculate the two unknown isolation resistances. The first measurement is taken with SW1 open and SW2 closed. The second measurement is taken with SW1 closed and SW2 closed. With these two measurements it is possible to solve the system of equations and calculate RISOP and RISON.

In the following example the voltage on the chassis ground is arbitrarily referred to as VRISONx.

For the first ADC measurement SW2 is closed as shown below and the following equations relate the ADC voltage to the other parameters in the system in this condition:

  • VADC1 measurement 1: SW1 open, SW2 closed
Equation 1. V R I S O N 1 = V P A C K   × R I S O N | | ( R D I V 1 + R D I V 2 ) R I S O P + ( R I S O N | | R D I V 1 + R D I V 2 )
Equation 2. V A D C 1 = V R I S O N 1   ×   R D I V 2 R D I V 1 + R D I V 2
GUID-AE3038E1-AEAF-4A60-9F8C-FF11DAEAF18E-low.svg Figure 9-4 Battery V- Reference Switch Positions for ADC1 Measurement

For the second ADC measurement SW1 and SW2 are closed as shown below and the following equations relate the ADC voltage to the other parameters in the system in this condition:

  • VADC2 measurement 2: SW1 closed, SW2 closed
Equation 3. V R I S O N 2 = V P A C K   ×   R I S O N | | ( R D I V 1 + R D I V 2 ) ( R I S O P | | R 3 ) + ( R I S O N | | ( R D I V 1 + R D I V 2 )
Equation 4. V A D C 2 = V R I S O N 2   ×   R D I V 2 R D I V 1 + R D I V 2
GUID-9BDCE7F9-072F-4987-B2B7-8036A90046D8-low.svg Figure 9-5 Battery V- Reference Switch Positions for ADC2 Measurement

Chassis Ground Reference Example

A Chassis Ground Reference architecture is shown below. SW1 and SW2 initiate connections to the PACK+ and PACK-, and enable their corresponding measurement paths to their ADCs through their corresponding resistor dividers. RDIV1, RDIV2, RDIV3, and RDIV4 scale the measured voltages down to the appropriate ADC ranges.

This first measurement is taken with SW1 closed and SW2 open and the second measurement is taken with SW1 open and SW2 closed.

  • VADC0: SW1 closed, SW2 open
Equation 5. V A D C 1 = V R D I V 2 = V P A C K ( R I S O P | | ( R D I V 1 + R D I V 2 ) ) ( R I S O P | | ( R D I V 1 + R D I V 2 ) + R I S O N ) × R D I V 2 R D I V 1 + R D I V 2
  • VADC1: SW1 open, SW2 closed
Equation 6. V A D C 2 = V R D I V 3 = - V P A C K ( R I S O N | | ( R D I V 3 + R D I V 4 ) ) ( R I S O N | | ( R D I V 3 + R D I V 4 ) ) + R I S O P ) × R D I V 3 R D I V 3 + R D I V 4
GUID-BB426EB5-4643-4118-8306-3E32FA651C0E-low.svg Figure 9-6 Chassis Ground Reference Switch Positions for ADC1 Measurement
GUID-01FC2571-B62E-4639-A5D1-8F74D6ED4A15-low.svg Figure 9-7 Chassis Ground Reference Switch Positions for ADC2 Measurement

Battery V- Reference and Chassis Ground Reference Architectures with the TPSI2140-Q1

The circuits in Figure 9-8 and Figure 9-9 demonstrate how to connect the TPSI2140-Q1 as a switch in each of the architectures above.

GUID-20220203-SS0I-FWZR-RGPR-PXJ6JPBPDVJP-low.svg Figure 9-8 TPSI2140-Q1 Insulation Resistance Monitoring – Battery V- Reference
GUID-20220203-SS0I-5RSG-PFZF-WB3FXDTPWRN7-low.svg Figure 9-9 TPSI2140-Q1 Insulation Resistance Monitoring – Chassis Ground Reference