SLVSFZ8A November   2021  – January 2026 DRV8231A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
    7. 6.7 Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Bridge Control
      2. 7.4.2 Current Sense and Regulation (IPROPI)
        1. 7.4.2.1 Current Sensing
        2. 7.4.2.2 Current Regulation
      3. 7.4.3 Protection Circuits
        1. 7.4.3.1 Overcurrent Protection (OCP)
        2. 7.4.3.2 Thermal Shutdown (TSD)
        3. 7.4.3.3 VM Undervoltage Lockout (UVLO)
    5. 7.5 Device Functional Modes
      1. 7.5.1 Active Mode
      2. 7.5.2 Low-Power Sleep Mode
      3. 7.5.3 Fault Mode
    6. 7.6 Pin Diagrams
      1. 7.6.1 Logic-Level Inputs
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Brush DC Motor
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Motor Voltage
          2. 8.2.1.2.2 Motor Current
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Stall Detection
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Stall Detection Timing
          2. 8.2.2.2.2 Stall Threshold Selection
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Relay Driving
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Control Interface for Single-Coil Relays
          2. 8.2.3.2.2 Control Interface for Dual-Coil Relays
        3. 8.2.3.3 Application Curves
      4. 8.2.4 Multi-Sourcing with Standard Motor Driver Pinout
    3. 8.3 Current Capability and Thermal Performance
      1. 8.3.1 Power Dissipation and Output Current Capability
      2. 8.3.2 Thermal Performance
        1. 8.3.2.1 Steady-State Thermal Performance
        2. 8.3.2.2 Transient Thermal Performance
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Bulk Capacitance
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Community Resources
    4. 9.4 Trademarks
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.4.3.1 Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge are disabled. The driver re-enables after the OCP retry period (tRETRY) has passed. If the fault condition is still present, the cycle repeats as shown in Figure 7-6.

DRV8231A OCP Operation Figure 7-6 OCP Operation

Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding results in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so overcurrent protection functions regardless of VREF and IPROPI settings.