SLVSGG6D April   2022  – September 2026 TPS25981

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
      1.      15
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO and UVP)
      2. 7.3.2 Overvoltage Lockout (OVLO)
      3. 7.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 7.3.3.1 Slew Rate (dVdt) and Inrush Current Control
        2. 7.3.3.2 Circuit-Breaker During Steady-State
        3. 7.3.3.3 Active Current Limiting During Start-Up
        4. 7.3.3.4 Short-Circuit Protection
      4. 7.3.4 Analog Load Current Monitor
      5. 7.3.5 Overtemperature Protection (OTP)
      6. 7.3.6 Fault Response and Indication (FLT)
      7. 7.3.7 Power Good Indication (PG)
      8. 7.3.8 Quick Output Discharge (QOD)
      9. 7.3.9 Reverse Current Blocking FET Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Single Device, Self-Controlled
        1. 8.1.1.1 Other Variations
      2. 8.1.2 Parallel Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Device Selection
        2. 8.2.2.2 Setting Output Voltage Rise Time (tR)
        3. 8.2.2.3 Setting Overcurrent Threshold (ILIM)
        4. 8.2.2.4 Setting Overcurrent Blanking Interval (tITIMER)
        5. 8.2.2.5 Voltage Drop
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Transient Protection
      2. 8.3.2 Output Short-Circuit Measurements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.7 Power Good Indication (PG)

The TPS259814x provides an active high digital output (PG) which serves as a power good indication signal and is asserted high when the device is in steady-state and ready to deliver power. The PG is an open-drain pin and must be pulled up to an external supply.

After power up, PG is pulled low initially. The device initiates a inrush sequence in which the FET is turned on in a controlled manner. When the FET gate voltage reaches the full overdrive indicating that the inrush sequence is complete, the PG is asserted after a de-glitch time (tPGA).

PG is de-asserted if at any time the FET is turned off. The PG de-assertion de-glitch time is tPGD.

TPS25981 TPS25981xx PG Timing Diagram Figure 7-7 TPS25981xx PG Timing Diagram
Table 7-3 TPS25981xx PG Indication Summary

Event

Protection Response

PG Pin

PG Delay

Undervoltage (UVP or UVLO)

Shutdown

L

Overvoltage (OVLO)

Shutdown

L

tPGD

Steady-state

NA

H

tPGA

Transient overcurrent

NA

H

Persistent overload

Circuit-breaker

L

tITIMER + tPGD

Output short-circuit to GND

Fast-trip followed by current limit

L

tPGD

ILM pin open

Shutdown

L

tITIMER + tPGD

ILM pin shorted to GND

Shutdown

L

tPGD

Overtemperature

Shutdown

L

tPGD

When there is no supply to the device, the PG pin is expected to stay low. However, there is no active pulldown in this condition to drive this pin all the way down to 0V. If the PG pin is pulled up to an independent supply which is present even if the device is unpowered, there can be a small voltage seen on this pin depending on the pin sink current, which is a function of the pullup supply voltage and resistor. Minimize the sink current to keep this pin voltage low enough not to be detected as a logic HIGH by associated external circuits in this condition.