SLVSGX0C May   2022  – December 2025 ESD762

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings—JEDEC Specification
    3. 5.3 ESD Ratings—IEC Specification
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics – ESD762 (DBZ)
    8. 5.8 Typical Characteristics – ESD762 (DXA)
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Temperature Range
      2. 6.3.2 IEC 61000-4-5 Surge Protection
      3. 6.3.3 IO Capacitance
      4. 6.3.4 Dynamic Resistance
      5. 6.3.5 DC Breakdown Voltage
      6. 6.3.6 Ultra Low Leakage Current
      7. 6.3.7 Clamping Voltage
      8. 6.3.8 Industry Standard Leaded Packages
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.3.2 IEC 61000-4-5 Surge Protection

The IO pins can withstand surge events up to 2.5A (8/20µs waveform) for the ESD762. An ESD-surge clamp diverts this current to ground.